Semiconductor Conductive Line Layout for High Integration Density
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Solution Overview
Problem
The photolithography process has limitations in forming fine patterns with reduced line widths and spacing widths, necessitating advanced technologies like double patterning and spacer patterning for highly integrated semiconductor devices, which require efficient layout schemes for metal lines and contact pads in narrow areas.
Innovation Solution
A semiconductor device layout where conductive lines are grouped and arranged in parallel, with contact pads positioned at opposite ends of each group to avoid overlap, and a manufacturing method involving photoresist patterns, spacers, and hard mask layers to form conductive lines and pads efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If photolithography process is used to reduce line widths and spacing widths, then integration density is improved, but manufacturing precision deteriorates due to resolution limits
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation into multiple stages through double patterning. First, initial patterns are formed using photolithography, then spacers are deposited and patterned to create additional fine patterns. This multi-stage approach allows achieving finer line widths and spacing that exceed the resolution limit of single-step photolithography, thereby improving integration density while maintaining manufacturing precision.
2Quantity of substance
If more conductive lines and contact pads are arranged in narrow area, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent employs asymmetry in the layout arrangement where contact pads are positioned at opposite ends of conductive line groups rather than symmetrically distributed. Specifically, first contact pads are coupled to ends of conductive lines in a first direction while second contact pads are coupled to ends in a second direction opposite to the first. This asymmetric arrangement optimizes space utilization and reduces overlap, enabling higher integration density without excessive layout complexity.
3Manufacturing precision
If contact pads are positioned to avoid overlap, then manufacturing precision is improved, but area occupied by contact pads increases
Solution Approach 1:
The patent resolves the area conflict by utilizing directional arrangement in multiple dimensions. Contact pads are arranged in opposite directions (first direction and second direction) at the ends of conductive line groups. This dimensional approach allows contact pads to be distributed more efficiently across the available area, avoiding overlap while minimizing the total area occupied, thus maintaining both manufacturing precision and space efficiency.
Data Source
AI summary
A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.