Semiconductor Conductive Lines Sub-Resolution Width
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Solution Overview
Problem
Existing methods for disposing interconnection lines in semiconductor devices, such as word lines and bit lines, face challenges in securing a sufficient contact region and maintaining line width due to the limitations of lithography resolution, particularly as transistor sizes decrease.
Innovation Solution
The semiconductor device incorporates conductive lines with sub-resolution line widths extending across core regions, with contact pads arranged diagonally to ensure electrical connection and sufficient spacing, allowing for improved integration density and preventing misalignment issues during lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If word lines extend only in one direction from the memory cell array region, then a sufficient region for the contact portion may be secured, but it may be difficult to secure a region for the contact region when the word lines have a line width smaller than the resolution limit in a lithography process
Solution Approach 1:
The conductive lines extend in both first and second directions (orthogonal dimensions) from the cell array region to reach first and second core regions, respectively. This two-directional extension allows the contact regions to be distributed across different spatial dimensions, resolving the conflict between maintaining fine line widths and securing sufficient contact region area.
2Productivity
If the size of the cell transistor is reduced to increase integration density, then integration efficiency is improved, but it is increasingly difficult to dispose interconnection lines required for operating the cell transistor
Solution Approach 1:
Interconnection lines are disposed in multiple directions (first and second directions) rather than confined to a single direction. This multi-dimensional routing approach provides additional spatial pathways for interconnection lines, enabling efficient signal routing even as transistor sizes are reduced to increase integration density.
Solution Approach 2:
The interconnection structure is segmented into multiple conductive lines extending in different directions to different core regions. This segmentation allows independent routing and connection management, simplifying the overall interconnection disposal while maintaining high integration density.
3Manufacturing precision
If conductive lines have fine line widths below lithography resolution limits, then integration density is enhanced, but misalignment issues during lithography may occur
Solution Approach 1:
Contact pads are arranged in different directions (first and second directions) relative to the cell array region, creating spatial separation in multiple dimensions. This multi-dimensional arrangement increases the process margin for alignment, reducing the risk of misalignment during lithography even when conductive lines have fine widths below resolution limits.
Data Source
AI summary
A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.