Semiconductor Conductive Lines Sub-Resolution Patterning
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming ultrafine patterns with line widths and spaces below the resolution limit of photolithography processes, limiting the density and speed of semiconductor devices.
Innovation Solution
A method involving double patterning technology (DPT) is employed to form conductive lines and pads with sub-resolution limit dimensions, using a mask pattern with selected shapes and applying photolithography, spacer layers, and etching processes to achieve precise line widths and spacings, allowing for higher density and speed in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography process is used, then manufacturing process is simple, but line width and space cannot be formed below resolution limit
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation into multiple discrete steps: forming mandrel patterns, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This multi-stage segmentation enables achieving sub-resolution line widths and spaces that cannot be obtained through single-step photolithography, directly resolving the contradiction between manufacturing precision and process complexity.
2Manufacturing precision
If double patterning technology is used, then line width and space below resolution limit can be formed, but manufacturing process becomes complex
Solution Approach 1:
The patent employs self-service principles through self-aligned spacer formation where the first and second spacers automatically position themselves relative to the mandrel patterns and each other. The spacer deposition and etching processes are self-aligned, eliminating the need for additional alignment steps and reducing manufacturing complexity despite the multi-step nature of the process.
Solution Approach 2:
The patent utilizes parameter changes by varying the thickness of spacer layers (first spacer layer thickness equal to target line width, second spacer layer thickness equal to target pad width) and controlling etching selectivity between different materials. These parameter adjustments enable precise control of final pattern dimensions while maintaining ease of manufacture through standardized process parameters.
3Quantity of substance
If ultrafine patterns are formed, then device density increases, but photolithography resolution limit is exceeded
Solution Approach 1:
The patent transitions from two-dimensional photolithography patterning to three-dimensional spacer-based patterning. By depositing vertical spacer layers on mandrel structures and using selective etching, the process achieves sub-resolution horizontal dimensions through vertical dimension control, enabling ultrafine patterns with higher device density while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-density semiconductor devices with ultrafine conductive lines and pads, overcoming the limitations of traditional photolithography by achieving patterns below the resolution limit, thereby enhancing device density and operational speed.
Implementation Method 1
applying photolithography, spacer layers, and etching processes to achieve precise line widths and spacings
Implementation Method 2
forming a first spacer layer on the mask pattern and the insulating layer
Implementation Method 3
etching the insulating layer to form the second mask pattern, etching the conductive layer to form conductive lines
Data Source
AI summary
A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.