Semiconductor Conductive Pattern Fabrication Using Auxiliary Masks
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in efficiently forming patterns of different widths and spacings, which affects the uniformity and alignment of conductive patterns in semiconductor devices, such as flash memory devices.
Innovation Solution
A method involving the formation of sacrificial patterns, spacers, and auxiliary masks is used to etch mask layers and underlying layers, allowing for the creation of conductive patterns with varying widths and uniform spacings, enabling precise feature formation in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-mask patterning is used, then the fabrication process is simple, but it is impossible to form patterns with uniform spacing and varying widths simultaneously
Solution Approach 1:
The fabrication process is divided into multiple independent stages: forming first patterns with initial spacing, depositing spacers on sidewalls, removing sacrificial material, and forming second patterns with different widths. Each stage independently contributes to the final pattern geometry, enabling precise control over both spacing and width variations without compromising overall process manageability
Solution Approach 2:
Sacrificial patterns are formed in advance before the final conductive patterns. These preliminary sacrificial structures serve as templates that define the spacing between final patterns. By pre-establishing the spacing framework using sacrificial material, the subsequent formation of conductive patterns with varying widths can proceed without compromising the uniform spacing requirement
2Adaptability or versatility
If multiple etching steps with different masks are used to form patterns of different widths, then pattern diversity is achieved, but alignment uniformity and spacing consistency deteriorate
Solution Approach 1:
Spacers serve as intermediary structures that mediate between the first patterns and the final conductive patterns. The spacers are deposited conformally on the sidewalls of first patterns, ensuring that the spacing between adjacent conductive patterns is determined by the spacer thickness rather than by direct mask alignment. This intermediary approach decouples the spacing control from the width variation control, allowing both requirements to be satisfied simultaneously
Solution Approach 2:
Different regions of the patterned structure are given different properties: the spacing between patterns is controlled by the uniform thickness of spacers deposited on sidewalls, while the width of individual conductive patterns is controlled by the local geometry of sacrificial patterns and auxiliary masks. This local differentiation of control mechanisms enables simultaneous achievement of uniform spacing and varied widths
3Manufacturing precision
If auxiliary masks are formed over spacer patterns, then precise feature formation is enabled, but the fabrication process complexity increases
Solution Approach 1:
The spacer structures automatically define the positions and dimensions of auxiliary masks through conformal deposition on their sidewalls. When auxiliary masks are formed, they self-align to the spacer patterns without requiring additional alignment steps or complex positioning procedures. This self-service mechanism maintains high fabrication efficiency while achieving precise feature formation, as the spacers act as self-aligning templates for subsequent etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the simultaneous formation of conductive patterns with uniform spacing and varying widths, improving the alignment and density of features in semiconductor devices, enhancing the performance and reliability of devices like flash memory.
Implementation Method 1
The mask layer is etched using the first and second patterns and the first and second auxiliary masks as an etch mask to thereby form a first upper mask of first upper mask pattern features below the first patterns, respectively, and a second upper mask of a second upper mask pattern feature below the second pattern
Implementation Method 2
sidewalls of the second auxiliary mask are disposed on the first and second portions of the second pattern, respectively
Data Source
AI summary
A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask.