Semiconductor Conductive Pattern Oxidation for Insulation

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Solution Overview

Problem

Three-dimensional semiconductor devices face challenges in achieving low resistance due to the arrangement of conductive patterns between interlayer insulating layers, which are difficult to insulate effectively, leading to potential bridge errors and increased resistance.

Innovation Solution

The semiconductor device includes conductive patterns that fill interlayer spaces between insulating layers and are covered with an isolation layer formed by oxidizing a portion of the conductive patterns, which deviates from the interlayer spaces, thereby reducing resistance and preventing bridge errors by creating an insulating distance between layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conductive patterns are arranged between interlayer insulating layers in three-dimensional semiconductor devices, then device integration is achieved, but resistance increases and insulation becomes difficult

Engineering Contradiction:
Improvedevice integrationVSAvoidinsulation quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The conductive pattern extends beyond the interlayer space before the isolation layer is formed, preparing the structure in advance for subsequent oxidation processes that will create the insulating barrier

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation layer acts as an intermediary substance formed by oxidizing the conductive pattern material, creating an insulating barrier between adjacent conductive patterns on different layers while maintaining electrical connection through the channel layer

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If conductive patterns are stacked to be spaced apart from one another, then three-dimensional structure is formed, but resistance decreases

Engineering Contradiction:
Improvethree-dimensional structureVSAvoidresistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The conductive pattern extends in the vertical dimension beyond the interlayer space, allowing electrical connection through the channel layer while maintaining spatial separation between patterns on different layers

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If conductive patterns deviate from interlayer spaces, then electrical connection is improved, but bridge errors increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidbridge errors
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The conductive pattern material is oxidized to form an isolation layer, converting the potentially harmful extended conductive material that could cause bridge errors into a beneficial insulating structure that prevents such errors while allowing electrical connection through the channel layer

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the resistance of the conductive patterns and prevents bridge errors by ensuring proper insulation between conductive patterns on different layers, enhancing the overall performance of the semiconductor device.

Implementation Method 1

forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10734407B2Manufacturing method of semiconductor device
Publication Date: 2020.08.04 MIMIRIP LLC
  • US10734407B2 patent drawing
  • US10734407B2 patent drawing
  • US10734407B2 patent drawing

AI summary

A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.