Semiconductor Device Conductive Pattern Formation

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Solution Overview

Problem

The photolithography process for forming conductive patterns in semiconductor devices is complex and costly due to multiple process steps, which complicates manufacturing and affects mechanical and electrical reliability.

Innovation Solution

A semiconductor device and method involving a first conductive layer to uniform the surface of a semiconductor structure, allowing conductive patterns to be formed using a roll printing process, followed by an electroless plating layer to enhance adhesion and reliability, reducing manufacturing complexity and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If photolithography process is used to form conductive patterns, then conductive patterns such as bumps and redistribution lines can be formed, but the manufacturing process becomes complex and costly due to multiple process steps

Engineering Contradiction:
Improvemechanical and electrical reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates unnecessary process steps from the traditional photolithography method. Specifically, it removes the requirements for forming separate adhesive layers and seed layers, and eliminates the need for photoresist application, exposure, and development processes. The conductive patterns are formed directly by depositing conductive material through openings in the insulating layer, significantly simplifying the manufacturing process while maintaining reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary actions by pre-forming openings in the insulating layer at the desired pattern locations before depositing the conductive material. This preliminary structuring of the insulating layer with openings eliminates the need for subsequent photoresist patterning steps, as the openings themselves define where the conductive patterns will be formed, thereby simplifying the overall process

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If photolithography process is used to form conductive patterns, then conductive patterns can be formed, but manufacturing cost increases due to many process steps

Engineering Contradiction:
Improveconductive pattern formation precisionVSAvoidmanufacturing ease and cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates costly process steps including photoresist application, exposure, development, and removal. By forming conductive patterns through direct deposition into pre-formed openings, it removes the need for expensive photolithography equipment and materials while maintaining precise pattern formation through controlled material deposition into the opening structures

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive photolithography materials (photoresist, adhesives, seeds) with a simpler conductive material deposition process. The openings in the insulating layer serve as permanent templates that eliminate the need for disposable photoresist layers, reducing material costs and simplifying the manufacturing process

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If traditional photolithography process is used, then conductive patterns can be formed, but manufacturing time increases due to sequential process steps

Engineering Contradiction:
Improveconductive pattern reliabilityVSAvoidmanufacturing productivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple sequential process steps into a single integrated process. The formation of openings in the insulating layer and the deposition of conductive material are combined into one continuous manufacturing flow, eliminating the sequential nature of photoresist application, exposure, development, electroplating, and photoresist removal. This integration significantly reduces manufacturing time while maintaining pattern reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The openings in the insulating layer are pre-formed with precise dimensions and positions, serving as built-in templates that guide conductive material deposition. This preliminary structuring eliminates the need for time-consuming photoresist processing steps and allows direct formation of conductive patterns, thereby improving manufacturing productivity without sacrificing reliability

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach simplifies the manufacturing process, improves mechanical and electrical reliability by minimizing defects, and reduces costs compared to traditional photolithography methods while maintaining high performance.

Implementation Method 1

forming a first conductive layer in the openings to make the one surface of the semiconductor structure more uniform

Methodology Applied
Scientific EffectElectroless plating:

Implementation Method 2

a second conductive layer which may be an electroless plating layer

Methodology Applied
Scientific EffectElectroless plating:

Data Source

PatentUS8889481B2Semiconductor device and method for manufacturing the same
Publication Date: 2014.11.18 SK HYNIX INC
  • US8889481B2 patent drawing
  • US8889481B2 patent drawing
  • US8889481B2 patent drawing

AI summary

A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor structure including the first conductive layers.