Semiconductor Conductive Patterns for Exposure Margin
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Solution Overview
Problem
The development of exposure equipment for forming fine patterns in semiconductor devices has not kept pace with the increasing integration and miniaturization of semiconductor devices, making it difficult to secure fine photoresist patterns, particularly in the limited cell region of memory chips.
Innovation Solution
The semiconductor device employs spacer patterning technology to form conductive patterns with specific shapes and pitches in different regions, including S-shaped and oval shapes, to improve exposure process margins and prevent failures like bridges between patterns, thereby enhancing critical dimension uniformity and patterning efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing exposure equipment is used to form photoresist patterns, then the manufacturing process is simple, but the resolution is insufficient to secure fine patterns
Solution Approach 1:
The patent applies segmentation by dividing a single exposure process into multiple exposure steps (first exposure and second exposure). The first exposure forms an initial pattern with relaxed resolution requirements, and the second exposure adds finer details. This multi-stage approach allows the final pattern to achieve higher precision than any single exposure step could produce alone, effectively overcoming the resolution limit of existing exposure equipment.
2Manufacturing precision
If the cell region area is increased to maintain memory capacity, then more patterns can be formed, but the critical dimension is reduced making patterning more difficult
Solution Approach 1:
The patent segments the patterning process into multiple exposure and development steps. The first exposure forms a preliminary pattern, followed by a second exposure that refines the critical dimensions. This segmented approach allows better control over CD uniformity even when patterns are densely packed in the cell region, addressing the challenge of maintaining precision in high-density layouts.
Solution Approach 2:
The first exposure and development step performs a preliminary action by forming an initial pattern structure before the second exposure. This preliminary pattern serves as a foundation that improves the uniformity of critical dimensions in subsequent processing, making the final fine patterning more reliable even in high-density cell regions.
3Manufacturing precision
If double exposure etch technology is used to form fine patterns, then pattern resolution is improved, but process complexity increases
Solution Approach 1:
The patent segments the patterning into two distinct exposure steps with different photoresist layers and development conditions. The first exposure uses a first photoresist layer with specific properties, and the second exposure uses a second photoresist layer with different properties optimized for fine pattern formation. This segmentation allows each step to be optimized independently, achieving high resolution while managing process complexity through systematic division of tasks.
Data Source
AI summary
The semiconductor device includes a semiconductor substrate including a first region straightly connected to a cell string region and a second region adjacent to the first region, a first conductive pattern having a first pitch in the first region, a second conductive pattern connected to the first conductive pattern in the first region and having a structure in which S shaped characters are continuously connected in a zigzag shape, and a third conductive pattern spaced from the second conductive pattern in the second region and having an essentially oval shape in which a central portion thereof is divided. An exposure process margin is improved in an X-decoder region and a failure such as a bridge is reduced to improve characteristics of the semiconductor device.