Semiconductor Conductive Patterns for Resistance and Power Efficiency
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Solution Overview
Problem
Next-generation semiconductor memory devices face challenges in achieving improved resistance characteristics and power efficiency, particularly in maintaining data storage without power supply, as existing materials exhibit varying resistance based on current or voltage and may not integrate well for high-density structures.
Innovation Solution
A semiconductor device structure featuring a lower conductive pattern, an intermediate conductive pattern with distinct portions, and an upper conductive pattern, where the intermediate pattern is vertically aligned and has a greater width than the lower pattern, enhancing electrical connectivity and resistance characteristics through a buffer and spacer pattern configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional conductive pattern structure is used, then the device structure is simple, but the resistance characteristics are insufficient for high-performance memory devices
Solution Approach 1:
The conductive pattern is segmented into three distinct portions: a lower conductive pattern, an intermediate conductive pattern, and an upper conductive pattern. Each portion has specific dimensional characteristics (the intermediate pattern has greater width and extends to a higher level) that collectively improve resistance characteristics while maintaining manageable structural complexity through modular design
Solution Approach 2:
The intermediate conductive pattern extends in the vertical dimension to a higher level than the lower conductive pattern, creating a three-dimensional conductive structure. This dimensional transition improves electrical connectivity and resistance characteristics by providing additional conduction pathways and optimizing interfacial contact areas
2Use of energy by moving object
If materials with varying resistance based on current or voltage are used, then power consumption can be reduced, but data storage reliability without power supply is compromised
Solution Approach 1:
The conductive pattern structure utilizes controlled changes in dimensional parameters (width, height, position) and material composition to achieve optimal resistance characteristics. The intermediate conductive pattern's greater width and elevated position create specific resistance profiles that enable low-power operation while maintaining stable data storage states through optimized electrical properties
3Productivity
If the vertical height between conductive patterns is reduced, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The conductive structure is divided into three separately formable portions with clear interface definitions. The intermediate conductive pattern serves as a distinct layer that can be manufactured with controlled thickness and position, enabling reduced overall vertical height while maintaining manufacturability through step-by-step fabrication processes
Solution Approach 2:
The intermediate conductive pattern acts as a mediator layer between the lower and upper conductive patterns. This intermediate layer provides a buffered interface that accommodates manufacturing variations, allowing reduced vertical spacing while maintaining alignment tolerance through its greater width and elevated position that create overlapping contact areas
Data Source
AI summary
A semiconductor device and an electronic system are provided. The semiconductor device includes a lower conductive pattern, and an intermediate conductive pattern on the lower conductive pattern. An upper conductive pattern is provided on the intermediate conductive pattern and is electrically connected to the intermediate conductive pattern. The intermediate conductive pattern includes a first portion and a second portion that extends from a part of the first portion and that is disposed at a higher level from the lower conductive pattern than the first portion. The upper conductive pattern is disposed on the first portion of the intermediate conductive pattern and has a top surface that is disposed at a higher level from the lower conductive pattern than the second portion of the intermediate conductive pattern.