Semiconductor Conductive Patterns with Asymmetric Spacing and Spacers
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming highly integrated patterns with minute pitches due to limitations in photolithography resolution, leading to the formation of bridges between conductive patterns and reduced yield.
Innovation Solution
The semiconductor device design includes conductive patterns with varying distances from the region boundary and the use of spacers and protruding insulating structures to prevent bridge formation, allowing for increased process margins and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If photolithography is used to form highly integrated patterns with minute pitches, then integration density increases, but bridge formation occurs between conductive patterns reducing yield
Solution Approach 1:
The conductive pattern formation process is segmented into multiple steps: first forming mandrels with initial spacing, then using spacers to define final conductive pattern positions. This segmentation allows precise control over pattern spacing, preventing bridge formation while maintaining high integration density.
Solution Approach 2:
Spacers are introduced as intermediary structures between mandrels and final conductive patterns. These spacers act as mediators that precisely control the spacing and positioning of conductive patterns, ensuring adequate separation to prevent bridges while enabling high-density integration.
2Area of stationary object
If conductive patterns are placed closer together to increase integration, then device area decreases, but process margin reduces leading to bridge formation
Solution Approach 1:
Mandrels are formed in advance with spacing that is larger than the final desired conductive pattern spacing. This preliminary action creates a buffer zone that accommodates subsequent spacer formation and alignment variations, maintaining adequate process margin even when final patterns are closely spaced.
Solution Approach 2:
The solution transitions from two-dimensional planar patterning to three-dimensional structure formation using vertical spacers. By utilizing the vertical dimension for spacer formation, the method achieves precise lateral spacing control without being constrained by photolithography resolution in the planar domain, thereby maintaining process margin at high integration densities.
Data Source
AI summary
A semiconductor device includes a substrate including first and second regions, which are arranged along a first direction. A first conductive pattern extends in the first direction in the first region. A second conductive pattern extends in the first direction in the first region. The second conductive pattern is spaced apart from the first conductive pattern. A first spacer extends between the first conductive pattern and the second conductive pattern along a sidewall of the first conductive pattern, a sidewall of the second conductive pattern, and a boundary between the first and second regions. A distance between the first conductive pattern and the second region is smaller than a distance between the second conductive pattern and the second region.