Semiconductor Package Conductive Post Intermetallic Compound Layer

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Solution Overview

Problem

Inconsistencies in the coefficient of thermal expansion (CTE) between semiconductor chips and main board materials can lead to stress concentration and joint failure in semiconductor packages, affecting reliability.

Innovation Solution

A semiconductor package design featuring a redistribution structure with a conductive post and encapsulation layer, where the conductive post includes an intermetallic compound (IMC) layer surrounded by the encapsulation layer, with the IMC layer's surface lower than the encapsulation layer's surface, to mitigate thermal stress and enhance joint reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive bumps are used to mount semiconductor packages on main boards, then electrical connection is achieved, but thermal stress concentration occurs due to CTE inconsistency between semiconductor chip and main board materials

Engineering Contradiction:

Improvejoint reliabilityVSAvoidthermal stress concentration

Core Design Contradiction:

ReliabilityVSStress or pressure

Solution Approach 1:

The patent introduces a conductive post with IMC layer as an intermediary component between the semiconductor chip and the conductive bump. This intermediate structure absorbs and distributes the thermal stress generated by CTE mismatch, preventing stress concentration at the joint interface and improving overall joint reliability

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The conductive post is constructed with composite material structure including an intermetallic compound (IMC) layer. This composite structure combines materials with different properties to create a gradient that accommodates thermal expansion differences between the semiconductor chip and the solder bump, thereby reducing thermal stress

Inventive Principle:

Principle #40Composite materials

2Reliability

If the IMC layer surface is exposed at the same level as the encapsulation layer, then electrical connection is facilitated, but the IMC layer becomes vulnerable to thermal stress and adhesive failure

Engineering Contradiction:

Improvejoint reliabilityVSAvoidthermal stress exposure

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The encapsulation layer is designed to extend beyond the IMC layer surface, creating a protective overhang before thermal stress occurs. This beforehand cushioning structure shields the vulnerable IMC layer from direct thermal stress exposure during subsequent reflow processes, preventing adhesive failure while maintaining electrical connectivity

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11705418B2Semiconductor package with conductive bump on conductive post including an intermetallic compound layer

Publication Date: 2023.07.18 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a semiconductor chip including a contact pad on an active surface, a first insulating layer on the active surface including a first opening that exposes the contact pad, a redistribution layer connected to the contact pad and extending to an upper surface of the first insulating layer, a second insulating layer on the first insulating layer and including a second opening that exposes a contact region of the redistribution layer, a conductive post on the contact region, an encapsulation layer on the second insulating layer and surrounding the conductive post, and a conductive bump on an upper surface of the conductive post. The conductive post includes an intermetallic compound (IMC) layer in contact with the conductive bump. An upper surface of the IMC layer is lower than an upper surface of the encapsulation layer.