Self-Aligned Contacts via Conductive Spacers in Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes face challenges in forming contacts due to image distortions from Optical Proximity Effects, leading to defects like voids in dielectric layers and increased parasitic resistances, especially when etching contact holes with varying depths and small width-to-height ratios.
Innovation Solution
The method involves forming continuous gate lines and conductive spacers on a semiconductor substrate, where the conductive spacers serve as self-aligned contacts, eliminating the need for etching contact holes and ensuring electrical isolation between devices by cutting or oxidizing the spacers after their formation, thus preventing voids and improving device performance with stressed materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact holes are etched to varying depths for gates and sources/drains simultaneously, then contact formation can be completed in one step, but etching precision deteriorates and defects like voids occur
Solution Approach 1:
The contact formation process is segmented into two independent steps: first forming gate contacts to the gate structure, then forming source/drain contacts to the source/drain regions. This segmentation allows each etching step to be optimized for its specific depth requirement, avoiding the precision problems of single-step variable-depth etching while maintaining overall process efficiency.
Solution Approach 2:
The gate contacts are formed in advance before the source/drain contacts. This preliminary action establishes a reference structure that enables self-aligned formation of subsequent source/drain contacts, ensuring precise positioning without requiring complex alignment procedures that would compromise etching precision.
2Device complexity
If contact holes with small width-to-height ratio are etched, then contact area is reduced, but etching difficulty increases and voids form
Solution Approach 1:
Gate contacts are formed as a preliminary structure with adequate dimensions and proper material composition. This pre-formed structure serves as a template that guides subsequent source/drain contact formation, ensuring that contacts are etched with appropriate dimensions and aspect ratios that avoid void formation while maintaining compact device layout.
Solution Approach 2:
The gate contact structure acts as an intermediary element between the gate and source/drain regions. It provides a stable reference structure that facilitates the formation of source/drain contacts with optimal geometry, mediating the relationship between compactness requirements and etching process capabilities.
3Manufacturing precision
If spacer material enters cuts during spacer formation, then self-aligned contacts are achieved, but voids and defects occur in dielectric layer
Solution Approach 1:
The formation of gate contacts and source/drain contacts is segmented into separate sequential steps rather than a single simultaneous process. This segmentation prevents spacer material from entering cuts and causing voids, while still achieving self-aligned contacts through the use of the previously formed gate contact structure as a alignment reference for subsequent source/drain contact formation.
4Manufacturing precision
If photolithography resolution is increased to handle high density patterns, then image distortion from OPE increases, but pattern fidelity deteriorates
Solution Approach 1:
The contact formation process is segmented into separate steps for gate contacts and source/drain contacts, each with their own patterning and etching operations. This segmentation allows each step to use optimized photolithography parameters and exposure conditions tailored to the specific pattern density and dimensions of that step, thereby reducing the impact of Optical Proximity Effects that would affect a single high-density pattern step.
Data Source
AI summary
There are provided a semiconductor device structure and a method for manufacturing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source/drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gates of respective unit devices, and isolated portions of the conductive spacer form contacts of respective unit devices. Embodiments of the present disclosure are applicable to manufacture of contacts in integrated circuits.