Semiconductor Conductor Gap via Barrier Discontinuity
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Solution Overview
Problem
As semiconductor line widths decrease, short-circuit problems between thin circuits in peripheral and core circuits occur due to issues with patterning M0 tungsten metal layers, necessitating an improved semiconductor structure and fabrication method to prevent such connections.
Innovation Solution
A semiconductor structure is fabricated with a substrate, interlayer dielectric layer, contact holes, a barrier layer, and conductive features, where a selective etching process creates a vertical trench and discontinuity in the barrier layer to separate conductive features and prevent short circuits, using a combination of lithographic and anisotropic etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the line width of the memory process is reduced to create finer traces, then the integration density is improved, but short-circuit problems occur between thin circuits
Solution Approach 1:
The patent applies segmentation by dividing the barrier layer into separate regions with discontinuities. The barrier layer is patterned to have gaps or discontinuities at specific locations between conductor features, creating isolated barrier regions that prevent electrical connection between adjacent conductors while maintaining the overall barrier function in other areas.
Solution Approach 2:
The patent applies local quality by creating non-uniform barrier layer structure with different properties in different locations. The barrier layer has continuous regions providing protection and discontinuous regions creating gaps for isolation. This local variation in barrier layer quality enables simultaneous achievement of conductor protection and short-circuit prevention in different spatial locations.
2Device complexity
If conventional lithographic and anisotropic etching processes are used, then the fabrication process is simple, but the barrier layer cannot be selectively removed to create the required gap structure
Solution Approach 1:
The patent introduces an intermediary material layer between the barrier layer and the conductor features. This intermediary layer serves as a sacrificial element that enables selective removal of the barrier layer. The intermediary layer is deposited, patterned, and then selectively removed to create the desired gap structure in the barrier layer without requiring direct etching of the barrier material itself.
Solution Approach 2:
The patent applies preliminary action by depositing and patterning the intermediary material layer before forming the final conductor features. This preliminary structure preparation enables subsequent selective barrier layer removal and gap formation to proceed with standard lithographic and etching processes, achieving complex results through preparatory structuring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents short circuits by creating a gap with a vertical trench and undercut structure, ensuring reliable separation of conductive features and enhancing the fabrication process for smaller memory circuitry.
Implementation Method 1
A selective etching process is performed to selectively etch the barrier layer thereby forming a gap between the first conductor feature and the second conductor feature
Implementation Method 2
A lithographic process and an anisotropic process are performed to etch the conductive layer, the barrier layer and the ILD layer
Data Source
AI summary
A semiconductor structure includes a contact plug located on a barrier layer in a contact hole; a first conductive feature integrally formed with the contact plug on the barrier layer; a second conductive feature disposed on the interlayer dielectric layer; and a gap between the first and second conductive features. The gap includes a vertical trench recessed into the interlayer dielectric layer, and a discontinuity in the barrier layer. The discontinuity extends below the second conductive feature to form an undercut structure.