Semiconductor Connection Bit Line Height Optimization
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Solution Overview
Problem
The challenge in semiconductor device design is to enhance electrical connections while maintaining compactness and high integration, as existing designs face issues with connection bit line height and surface level differences, which can lead to deterioration during etching processes.
Innovation Solution
The semiconductor device incorporates a connection bit line with a conductive semiconductor pattern that has a lower vertical thickness than the cell bit line, ensuring the top surface is at or below the cell bit line's level, and the connection metallic conductive pattern's height is equal to or greater than the cell's, improving electrical connections by minimizing etching-related deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the connection bit line height is increased to improve electrical connection, then electrical connection is improved, but the top surface level difference between cell bit line and connection bit line increases causing etching deterioration
Solution Approach 1:
The patent applies local quality by making the connection metallic conductive pattern taller than the cell metallic conductive pattern only in the connection region, while keeping the bit line top surfaces aligned. This localized height difference improves electrical connection in the connection region without creating surface level differences that would harm etching processes.
Solution Approach 2:
The patent resolves the contradiction by moving from a two-dimensional solution (increasing bit line height) to a three-dimensional solution with selective patterning. The connection metallic conductive pattern extends to a greater height than the cell metallic conductive pattern, allowing improved electrical connection while maintaining aligned top surfaces for etching process stability.
2Productivity
If design rules are reduced to achieve high integration and compactness, then device integration is improved, but electrical connection reliability deteriorates
Solution Approach 1:
The patent changes the height parameter of the metallic conductive patterns selectively in different regions. By making the connection metallic conductive pattern taller than the cell metallic conductive pattern, the patent improves electrical connection reliability without requiring increases in overall device dimensions, thus maintaining high integration.
3Reliability
If the connection metallic conductive pattern height is increased to improve electrical connection, then electrical connection is improved, but the vertical level difference between cell and connection regions increases
Solution Approach 1:
The patent applies local quality by differentiating the height of metallic conductive patterns between connection region and cell region. The connection metallic conductive pattern has greater height than the cell metallic conductive pattern, optimizing electrical connection locally without affecting the overall top surface alignment of bit lines.
Data Source
AI summary
A semiconductor device may include a substrate including a cell region and a connection region, a cell word line extending across the plurality of active regions in a first horizontal direction on the cell region of the substrate, a cell bit line including a cell metallic conductive pattern extending on the cell region of the substrate in a second horizontal direction, and a connection bit line including a connection metallic conductive pattern extending in the second horizontal direction on the connection region of the substrate. A top surface of the connection bit line may be located at a vertical level that is equal to or lower than a top surface of the cell bit line, and a height of the connection metallic conductive pattern in a vertical direction may be equal to or greater than a height of the cell metallic conductive pattern in the vertical direction.