Semiconductor Connection Element for 3D-IC Memory Density
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Solution Overview
Problem
Current three-dimensional-integrated circuit (3D-IC) memory techniques, such as fine pattern and multi-level cell (MLC) methods, face limitations in increasing memory capacity while maintaining cost-effectiveness, with the punch-and-plug technique being a promising but not fully optimized approach for enhancing memory density without significant cost increases.
Innovation Solution
The semiconductor device incorporates a connection structure with a connection element that intersects conductive lines, ensuring electrical connectivity while maintaining a coplanar surface with interlayer dielectric, allowing for efficient interconnection and increased memory capacity without excessive material usage or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern technique is used to increase memory capacity, then memory density is improved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical structures by forming bit lines and word lines in multiple stacked layers. Connection elements extend vertically through interlayer dielectric layers to connect conductive lines across different levels, enabling increased memory capacity without proportionally increasing manufacturing complexity or cost
2Quantity of substance
If multi-level cell (MLC) technique is used to increase memory capacity, then storage density is improved, but the number of bits per cell is limited
Solution Approach 1:
The patent implements a three-dimensional memory architecture where bit lines and word lines are arranged in multiple vertical layers. Connection elements penetrate through interlayer dielectric layers to establish electrical connections between conductive lines at different heights, enabling expanded memory capacity beyond the limitations of MLC by utilizing spatial dimensionality rather than just increasing bits per cell
3Quantity of substance
If punch-and-plug technique is used to increase memory capacity, then memory density is improved, but interconnection complexity increases
Solution Approach 1:
The patent forms connection elements that extend vertically through interlayer dielectric layers to connect bit lines and word lines across multiple stacked layers. This three-dimensional interconnection approach organizes complex connections in the vertical dimension, allowing increased memory capacity while managing interconnection complexity through structured layering rather than planar routing
4Adaptability or versatility
If connection element with wider width than contact plugs is used, then interconnection flexibility is improved, but material usage increases
Solution Approach 1:
The patent employs connection elements with varying cross-sectional dimensions optimized for different functional requirements. Connection elements have wider widths in regions requiring high interconnection flexibility and signal transfer, while maintaining narrower dimensions in other regions to reduce overall material consumption. This local optimization balances interconnection performance with material efficiency
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.