Semiconductor Structure With Voids In Connection Layer

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Solution Overview

Problem

The wafer dicing process in semiconductor manufacturing often damages chips due to stress propagation from the dicing region to the functional region, leading to cracks and performance issues, as there is no structure to prevent stress in the non-functional region between the functional and dicing regions.

Innovation Solution

A semiconductor structure and method involving a wafer with a functional region and a non-functional region, where a first dielectric layer with openings is formed, and a connection layer with voids is created to close the openings, reducing stress propagation and guiding it away from the functional region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a wafer dicing process is performed to separate the wafer into chips, then the wafer is divided into individual functional units, but stress propagates from the dicing region to the functional region causing chip damage

Engineering Contradiction:

Improvewafer dicing efficiencyVSAvoidchip integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A non-functional region is introduced as an intermediary zone between the functional region and dicing region. This non-functional region absorbs and isolates stress generated during dicing, preventing stress propagation to the functional region while allowing the dicing process to proceed efficiently.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The stress generated during the dicing process, which normally causes damage, is redirected into the non-functional region. By converting the harmful stress propagation into a contained stress concentration in the non-functional zone, the functional region is protected while maintaining dicing effectiveness.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If the non-functional region is used to absorb stress, then chip damage is reduced, but the wafer structure becomes more complex

Engineering Contradiction:

Improvechip damage resistanceVSAvoidwafer structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The wafer is segmented into distinct functional regions: functional region, non-functional region, and dicing region. This segmentation allows the non-functional region to serve as a dedicated stress absorption zone without complicating the overall wafer design, as each region has a clear, separate purpose.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the wafer are assigned different functional qualities: the functional region contains circuit structures, the non-functional region is designed for stress absorption, and the dicing region is optimized for cutting. This local differentiation allows stress management without adding complexity to the functional circuits.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11728286B2Semiconductor structure

Publication Date: 2023.08.15 SEMICON MFG INT (SHANGHAI) CORP

AI summary

A semiconductor structure is provided. The semiconductor structure includes a wafer having a functional region and a non-functional region surrounding the functional region; a first dielectric layer formed on the wafer; a first opening formed in the first dielectric layer on the non-function region of the wafer; and a first connection layer formed in the first opening. The first connection layer closes a top portion of the first opening and a first void is formed in the first connection layer in the first opening.