Semiconductor Connection Terminals for Multi-Structure Integration
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Solution Overview
Problem
Current semiconductor devices with wafer level Chip Scale/Size Package (CSP) face challenges in integration and miniaturization due to limited functionality of external terminals, making it difficult to form electronic components that integrate semiconductor devices with other structures.
Innovation Solution
Incorporating a connection terminal on the semiconductor substrate, in addition to external connection terminals, allows for mechanical or electrical connection with other functional structures, enabling integration and miniaturization of electronic components. This configuration includes relocated wiring, stress-relieving layers, and sealing resins to enhance reliability and prevent short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a wafer level CSP is applied to miniaturize the semiconductor device, then the device size is reduced, but the external terminals can only be used for circuit board packaging connections, making it extremely difficult to form an electronic component by integrating the semiconductor device with other structures
Solution Approach 1:
The patent applies multi-functionality by enabling external terminals to serve dual purposes: traditional circuit board packaging connections and new functions such as driving other structures (e.g., MEMS, crystal oscillators) or serving as connection terminals for additional electronic components. This resolves the contradiction by making the terminals adaptable to multiple uses without increasing device size.
Solution Approach 2:
The patent segments the terminal functions by providing both external terminals (for circuit board connections) and additional connection terminals (for integrating with other structures). This segmentation allows each terminal type to specialize in specific functions, resolving the versatility limitation while maintaining miniaturization.
2Device complexity
If external terminals are configured only for circuit board packaging connections, then the semiconductor device maintains a simple terminal configuration, but it becomes extremely difficult to integrate the semiconductor device with other functional structures into an electronic component
Solution Approach 1:
The patent makes terminals universal by enabling them to perform both traditional packaging connections and new integration functions with other structures, thereby improving adaptability without proportionally increasing complexity.
Solution Approach 2:
The patent adds a new dimension to terminal functionality by introducing connection terminals that enable vertical or lateral integration with other structures (e.g., MEMS, crystal oscillators), rather than only planar circuit board connections. This dimensional expansion of functionality resolves the integration difficulty.
3Adaptability or versatility
If additional connection terminals are provided on the semiconductor substrate, then integration with other functional structures becomes possible, but the device complexity increases
Solution Approach 1:
The patent uses multi-functionality to justify the added complexity: connection terminals are designed to serve multiple purposes including driving other structures, serving as connection terminals, and enabling functional checks, thereby making the increased complexity worthwhile for the gained versatility.
Solution Approach 2:
The patent merges the functions of external terminals and additional connection terminals into a unified terminal system that can handle both circuit board connections and integration with other structures, reducing the overall complexity compared to having completely separate terminal systems.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate having an active face; a first electrode provided on or above the active face; an external connection terminal provided on or above the active face and electrically connected to the first electrode; and a connection terminal provided on or above the active face of the semiconductor substrate.