Semiconductor Contact Structure With Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements for high-performance devices.
Innovation Solution
A semiconductor device design featuring a substrate with spaced active patterns, device isolation layers, source/drain patterns, active contacts, barrier patterns, and air gaps to enhance electrical connectivity and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demands for small pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent introduces a three-dimensional structure with vertical stacking of active patterns, source/drain patterns, and channel patterns. By transitioning from a two-dimensional planar layout to a three-dimensional stacked architecture, the device achieves higher integration density while maintaining adequate operational characteristics through controlled vertical spacing and electrical connectivity paths.
Solution Approach 2:
The patent employs intermediary structures including barrier patterns positioned between active contacts and source/drain patterns, and air gaps strategically placed between conductive elements. These intermediary features mediate the electrical interactions, controlling parasitic capacitance and ensuring proper electrical connectivity while maintaining compact device dimensions.
2Ease of operation
If active contact is directly connected to source/drain patterns, then electrical connectivity is simplified, but parasitic capacitance increases
Solution Approach 1:
The barrier pattern serves as an intermediary element positioned between the active contact and source/drain patterns. This barrier structure provides controlled electrical connectivity while simultaneously reducing parasitic capacitance by managing the electrical field distribution and preventing direct capacitive coupling between adjacent conductive elements.
Solution Approach 2:
The patent utilizes air gaps, which are essentially porous or void spaces, strategically positioned between conductive elements. These air gaps reduce parasitic capacitance by providing electrical insulation while maintaining compact device geometry, effectively eliminating harmful capacitive effects without compromising necessary electrical connectivity.
Data Source
AI summary
A semiconductor device may include a substrate including a first active pattern and a second active pattern, which are spaced apart from each other in a first direction parallel to a top surface of the substrate, a device isolation layer between the first and second active patterns, a first source/drain pattern disposed on the first active pattern, a second source/drain pattern disposed on the second active pattern, a first active contact disposed on the first and second source/drain patterns, a barrier pattern interposed between the first active contact and the first source/drain pattern and between the first active contact and the second source/drain pattern and extended into a space between the first active contact and the device isolation layer, and an air gap interposed between the first active contact and the barrier pattern. The first active contact may be electrically connected to the first and second source/drain patterns.