3D Semiconductor Contact Structure with High Aspect Ratio
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Solution Overview
Problem
Traditional contact structures in three-dimensional integrated circuits face limitations in process window of contact etching and are prone to electromigration issues due to their design following traditional planar processes, which restricts device density and electrical flow.
Innovation Solution
A novel contact structure with a cross-sectional aspect ratio of longer side to shorter side greater than 2:1 and a contact area ratio to via area greater than 25%, along with specific dimensions for the via and contact structures, such as a diameter less than 5 μm and spacing less than 0.5 μm, to enhance the process window and prevent electromigration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar contact structure design is used in 3D TSV wafers, then manufacturing simplicity is maintained, but process window of contact etching is limited and electromigration issues occur
Solution Approach 1:
The patent transitions from traditional planar (2D) contact structures to three-dimensional contact structures with vertical extensions. The contact structure includes a first contact portion on the TSV top surface and a second contact portion extending vertically downward into the TSV, creating a 3D configuration that increases contact area and improves electromigration resistance while managing the increased design complexity.
Solution Approach 2:
The contact structure is nested within the TSV structure, with the second contact portion extending into the TSV and potentially containing embedded structures. This nesting approach maximizes the use of vertical space and increases the effective contact area without significantly increasing the lateral footprint, thereby improving reliability while controlling device complexity.
2Productivity
If traditional contact structures are used, then device density is limited, but manufacturing process remains simple
Solution Approach 1:
By introducing vertical extensions and multi-level contact portions, the patent increases device density within the same lateral footprint. The three-dimensional contact structures allow more contacts to be packed in the same area, improving productivity while the manufacturing process window is enlarged through optimized etching parameters and multi-step etching processes.
Solution Approach 2:
The patent modifies critical parameters including contact structure geometry (aspect ratio, vertical height), material composition, and etching conditions. These parameter changes enable increased device density while simultaneously enlarging the process window for contact etching, making the manufacturing process more robust despite the increased structural complexity.
3Reliability
If contact area ratio is increased to prevent electromigration, then electrical flow capacity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes key parameters such as the aspect ratio of contact structures (vertical height to lateral width), the ratio of contact area to TSV area (specified as greater than 25%), and the dimensions of contact portions. These parameter optimizations increase the contact area ratio to prevent electromigration while establishing achievable manufacturing precision targets that balance reliability improvement with fabrication capability.
Data Source
AI summary
A semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a via defined in the substrate and extending from the first surface to the second surface; and a first plurality of contact structures on the first surface contacting the via. A cross section of each of the first plurality of contact structures parallel to the first surface has a first side and a second side, and a ratio of the longer side to the shorter side of the first side and the second side is more than about 2:1.