Semiconductor device structure and methods of forming the same
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits increases with scaling down, leading to higher manufacturing complexity and costs.
Innovation Solution
The semiconductor device structure incorporates a conductive feature formation process involving a blocking layer and barrier layer to reduce interface resistance, where the blocking layer prevents the barrier layer from forming on metallic surfaces, allowing direct contact between conductive features and reducing interface resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases
Solution Approach 1:
The patent segments the conductive feature formation into distinct stages: forming openings in the interlayer dielectric, depositing blocking layers on specific surfaces, depositing barrier layers, and filling with conductive material. This segmentation allows each step to be optimized independently, managing processing complexity while maintaining scaling benefits
Solution Approach 2:
The patent applies different materials and deposition conditions to different locations: blocking layers are deposited selectively on the ceiling and sidewalls of openings, while barrier layers are deposited on the conductive feature surfaces. This local differentiation enables precise control of interface properties at each location, addressing complexity through targeted rather than uniform processing
2Reliability
If conventional deposition methods are used for conductive features, then manufacturing is simpler, but interface resistance is higher
Solution Approach 1:
The patent introduces blocking layers as intermediary structures between the interlayer dielectric and the conductive barrier layers. These blocking layers (formed via SAMs and ALD) serve as mediators that control the deposition process and reduce interface resistance, improving electrical connectivity while the self-aligned nature of the process maintains manufacturing simplicity
Solution Approach 2:
The patent changes the deposition parameters by using atomic layer deposition (ALD) with specific blocking layers that have controlled thickness and material composition. This parameter control optimizes the interface between conductive features and surrounding materials, reducing interface resistance while maintaining processability through well-controlled deposition conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances the efficiency of conductive feature formation by reducing interface resistance, thereby improving the manufacturing process and overall performance of semiconductor devices.
Implementation Method 1
forming a blocking layer on the conductive feature. The blocking layer includes self-assembled monolayers (SAMs)
Implementation Method 2
atomic layer deposition (ALD) to reduce interface resistance
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a source/drain region and a first conductive feature disposed below the source/drain region. The first conductive feature is electrically connected to the source/drain region. The structure further includes a second conductive feature disposed over the source/drain region, and the second conductive feature is electrically connected to the source/drain region. The structure further includes a third conductive feature disposed on and in contact with a first portion of the second conductive feature and a dielectric layer disposed on and in contact with a second portion of the second conductive feature.