Semiconductor Contact Interface with Oxygen-Vacancy Complex Regions

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Solution Overview

Problem

As semiconductor integration density increases, existing manufacturing processes face challenges in achieving low contact resistance between semiconductor channel layers and source/drain terminals, which affects device performance.

Innovation Solution

A processing treatment is performed through contact openings in the semiconductor layer to form complex regions with higher oxygen vacancies and doping levels, reducing contact resistance by creating a self-aligned interface with the channel layer and source/drain terminals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor integration density is increased, then device integration capability is improved, but contact resistance between channel layer and source/drain terminals increases

Engineering Contradiction:
Improveintegration densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by creating complex regions with distinct properties at the interface between source/drain terminals and channel layer. These regions have higher doping levels and modified surface characteristics specifically where contact is needed, while the rest of the channel layer maintains its original properties. This localized modification reduces contact resistance without affecting overall device integration density.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes physical and chemical parameters of the semiconductor layer at the contact interface by forming complex regions with higher oxygen vacancies and doping levels. The processing treatment through contact openings modifies the semiconductor layer's electrical properties locally, transforming it from a uniform structure to one with gradient properties that optimize both conductivity and integration density.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If complex regions with higher doping levels are formed, then contact resistance is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the complex regions through a dedicated processing treatment step performed through contact openings before final source/drain terminal formation. This preliminary modification of the semiconductor layer ensures optimal contact properties are established in advance, simplifying subsequent manufacturing steps and reducing overall process complexity despite the added treatment step.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The processing treatment through contact openings enables the semiconductor layer to self-organize complex regions with appropriate doping levels and surface characteristics. The treatment modifies the layer properties in situ where needed, allowing the material to develop the required complex structure through the processing action itself rather than requiring multiple separate fabrication steps.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11749723B2Semiconductor device and manufacturing method thereof
Publication Date: 2023.09.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11749723B2 patent drawing
  • US11749723B2 patent drawing
  • US11749723B2 patent drawing

AI summary

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, complex regions, a source terminal and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The complex regions are respectively disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer.