Semiconductor Contact Structure With Dipole Layers for Low Resistance

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing contact resistance between source/drain regions and contact structures in FETs, which affects device performance due to high Schottky barrier heights, particularly with the scaling down of semiconductor devices.

Innovation Solution

The formation of dipole layers and ternary compound layers at interfaces between source/drain regions and silicide layers, achieved by doping the silicide layers with metals of lower electronegativity, reduces the Schottky barrier heights and contact resistances, thereby improving FET performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional silicide layers are used at source/drain contacts, then the manufacturing process is simple, but the Schottky barrier height is high resulting in high contact resistance

Engineering Contradiction:
Improvecontact resistanceVSAvoidcontact structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact structure is segmented into multiple functional layers: a dipole layer (first layer) and a ternary compound layer (second layer) are introduced between the source/drain region and the conventional silicide layer. This segmentation allows each layer to perform specific functions - the dipole layer reduces the Schottky barrier height through electric dipole moments, while the ternary compound layer provides optimal electrical and mechanical properties, collectively reducing contact resistance without compromising structural integrity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs composite material structures by combining different materials with complementary properties. The dipole layer uses materials with specific electronegativity differences to create favorable dipole moments, the ternary compound layer combines three elements to achieve unique electronic properties, and these are integrated with the conventional silicide layer to form a multi-material contact structure that achieves low contact resistance through synergistic material combinations

Inventive Principle:
Principle #40Composite materials

2Productivity

If the semiconductor device dimensions are scaled down, then the storage capacity and processing speed improve, but the contact resistance becomes more significant affecting device performance

Engineering Contradiction:
Improveprocessing speedVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by introducing specialized dipole and ternary compound layers specifically at the source/drain contact regions where low contact resistance is critical, while the rest of the device can continue to be scaled down. This localized enhancement ensures that the contact interfaces have optimized electrical properties (low Schottky barrier height) independent of the overall device scaling, allowing high-speed operation without being bottlenecked by contact resistance

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces contact resistances by 50% to 70% compared to FETs without these interfacial layers, enhancing the overall performance of FETs by lowering Schottky barrier heights.

Implementation Method 1

a dipole layer disposed at an interface between the ternary compound layer and the source/drain region

Methodology Applied
Scientific EffectDipole layer formation:

Implementation Method 2

reduces the Schottky barrier heights and contact resistances

Methodology Applied
Scientific EffectSchottky barrier height reduction:

Data Source

PatentUS11810960B2Contact structures in semiconductor devices
Publication Date: 2023.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11810960B2 patent drawing
  • US11810960B2 patent drawing
  • US11810960B2 patent drawing

AI summary

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.