Semiconductor Contact Structure Using ESL to Limit Lateral Etching

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to improve the formation and structure of interconnects to reduce device size, cost, and defects, while maintaining efficiency and minimizing current leakage.

Innovation Solution

The implementation of an etch-stop layer (ESL) made of aluminum oxide between inter-layer dielectric layers, combined with a multi-step etch process involving dry and wet etching techniques, helps control lateral etching and reduce pattern loading effects, thereby enhancing the precision and reliability of interconnect formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photolithographic and etching techniques are used to form interconnects, then interconnects can be formed to connect active and passive devices, but lateral etching occurs causing current leakage and reduced precision

Engineering Contradiction:
Improveinterconnect formation precisionVSAvoidcurrent leakage from lateral etching
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

An etch-stop layer is introduced as an intermediary between the inter-layer dielectric layers. This layer acts as a mediator that prevents lateral etching from propagating through the dielectric, thereby eliminating current leakage paths while allowing vertical etching to proceed for contact formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric structure is segmented by inserting an etch-stop layer at a specific depth. This segmentation creates distinct regions: the upper dielectric layer for insulation, the etch-stop layer for controlling etching, and the lower dielectric layer for structural support, thereby preventing uncontrolled lateral etching.

Inventive Principle:
Principle #1Segmentation

2Area of moving object

If device size is reduced to improve integration density, then more devices can be packed on the substrate, but interconnect formation becomes more complicated and prone to defects

Engineering Contradiction:
Improvedevice sizeVSAvoidinterconnect formation complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The etch-stop layer is deposited in advance before the interconnect formation process. This preliminary action establishes a controlled etching boundary that simplifies subsequent etching operations, reducing process complexity and defect formation even as device dimensions are reduced.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If multi-step etch process with dry and wet etching is used, then lateral etching is controlled and pattern loading effects are reduced, but process complexity increases

Engineering Contradiction:
Improvelateral etching controlVSAvoidetch process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The etching process parameters are changed by switching from a single etching method to a combination of dry and wet etching. The dry etching step provides anisotropic etching for vertical profiles, while the wet etching step provides isotropic etching for lateral release, thereby achieving precise lateral etching control despite increased process complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the reduction of current leakage from contacts by minimizing lateral etching of the etch-stop layer, leading to more efficient and reliable interconnects with fewer defects.

Implementation Method 1

extending the first opening through the etch-stop layer with a first wet etching process, the etch-stop layer being exposed to a first etching solution during the first wet etching process

Methodology Applied
Scientific EffectWet etching:

Implementation Method 2

the first etching solution including a dielectric protective agent for the first dielectric material

Methodology Applied
Scientific EffectProtective agent effect:

Implementation Method 3

etching a first opening through the second ILD with a first dry etching process

Methodology Applied
Scientific EffectDry etching:

Data Source

PatentUS12224204B2Semiconductor device and method
Publication Date: 2025.02.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12224204B2 patent drawing
  • US12224204B2 patent drawing
  • US12224204B2 patent drawing

AI summary

In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.