Semiconductor Contact Structure With Etch-Stop Layers for Low Capacitance
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Solution Overview
Problem
As semiconductor devices scale down, there is a need to reduce capacitance and improve electrical stability between contacts, while maintaining performance and reliability.
Innovation Solution
A semiconductor device is designed with a gate structure on a substrate, including a gate electrode, source/drain patterns on the side surface of the gate electrode, and specific etching stop film structures and via plugs to enhance contact connectivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch size of the semiconductor device is decreased to increase density, then device density is improved, but capacitance between contacts increases and electrical stability deteriorates
Solution Approach 1:
The patent introduces a multi-layer etching stop film structure (first etching stop film, second etching stop film, third etching stop film at different heights) and three-dimensional via plug configurations that extend in multiple dimensions. This dimensional approach allows contacts to be properly isolated and connected through vertical and horizontal pathways, reducing parasitic capacitance while maintaining small pitch spacing for high density.
Solution Approach 2:
The etching stop film structure is segmented into multiple layers at different heights (first, second, and third etching stop films), with via plugs strategically positioned at different levels. This segmentation creates distinct electrical isolation zones that reduce capacitance between adjacent contacts while allowing the overall device pitch to be minimized for increased density.
2Productivity
If the pitch size is decreased to increase device density, then device density is improved, but resistance between contacts increases
Solution Approach 1:
The patent employs via plugs that extend through multiple etching stop film layers at different heights, creating three-dimensional conductive pathways. This multi-dimensional approach allows electrical connections to be established through vertical and diagonal routes, reducing resistance by providing multiple parallel conduction paths while maintaining compact pitch dimensions for high device density.
Solution Approach 2:
The via plugs are nested within the multi-layer etching stop film structure, with first via plugs, second via plugs, and third via plugs positioned at different height levels within the stacked film architecture. This nesting arrangement allows conductive materials to be embedded throughout the vertical structure, creating low-resistance pathways that penetrate through multiple isolation layers while maintaining small horizontal pitch.
Data Source
AI summary
A semiconductor includes a gate structure on a substrate and including a gate electrode, a source/drain pattern on a side surface of the gate electrode, a source/drain contact connected to the source/drain pattern, a first etching stop film structure on the source/drain contact and the gate structure, the first etching stop film structure including a first lower etching stop film and a silicon nitride film on the first lower etching stop film, and a first via plug inside the first etching stop film structure and connected to the source/drain contact, wherein the first lower etching stop film includes aluminum, and wherein an upper surface of the silicon nitride film is on a same plane as an upper surface of the first via plug.