Semiconductor Contact Structures via Etching Stop Layer

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Solution Overview

Problem

The complexity of contact structures in integrated circuit structures, which require different depths and material layers, complicates the process of forming contact structures and negatively impacts manufacturing yield.

Innovation Solution

Incorporating an etching stop layer in a contact opening that penetrates the substrate, simplifying the integration of manufacturing steps for different contact structures by forming the etching stop layer on the gate structure, source/drain region, and sidewall/bottom of the contact opening, and using it in conjunction with an interlayer dielectric layer to facilitate the formation of contact structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If contact structures are formed to pass through different material layers and have different depths to meet complicated circuit requirements, then the adaptability of the contact structures is improved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvecontact structure adaptabilityVSAvoidcontact structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The contact structure is divided into multiple segments: a first contact structure passing through the first dielectric layer to reach the first conductive layer, and a second contact structure passing through the second dielectric layer to reach the second conductive layer. This segmentation allows each contact structure to be optimized independently for its specific depth and material layer requirements, improving adaptability while managing complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical stacking dimension with multiple dielectric layers and conductive layers at different heights. The first and second contact structures are positioned at different vertical levels, allowing the system to accommodate different contact depths and material layer configurations without increasing lateral complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If multiple etching steps are used to form contact structures at different depths, then the manufacturing precision is improved, but the productivity and manufacturing yield deteriorate

Engineering Contradiction:
Improvecontact structure precisionVSAvoidmanufacturing yield
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The first and second dielectric layers are formed with different etch selectivities before the contact structures are created. This preliminary differentiation of material properties allows subsequent etching processes to selectively remove each dielectric layer at different rates, enabling precise control of contact structure depths without requiring multiple separate etching steps, thus improving both precision and productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes etch selectivity as a key parameter to differentiate between the first and second dielectric layers. By controlling the etching parameters and material composition to achieve different etch rates, the system can form contact structures at different depths through a simplified process, improving manufacturing yield by reducing the number of process steps while maintaining precision

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20210167171A1Semiconductor device and manufacturing method thereof
Publication Date: 2021.06.03 UNITED MICROELECTRONICS CORP
  • US20210167171A1 patent drawing
  • US20210167171A1 patent drawing
  • US20210167171A1 patent drawing

AI summary

A semiconductor device includes a substrate, a gate structure, a source/drain region, a contact opening, an etching stop layer, an interlayer dielectric layer, and a first contact structure. The substrate includes a buried insulation layer, a semiconductor layer, and an isolation structure. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The isolation structure and the source/drain region are disposed in the semiconductor layer. The contact opening penetrates at least a part of the substrate. The etching stop layer is disposed on the gate structure, the source/drain region, a sidewall of the contact opening, and a bottom of the contact opening. The interlayer dielectric layer is disposed on the etching stop layer. The first contact structure penetrates the interlayer dielectric layer and the etching stop layer in the contact opening.