Semiconductor Contact Structure With Grain-Controlled Seed Layer

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Solution Overview

Problem

As semiconductor devices continue to scale down, the critical dimension (CD) of contacts decreases, leading to increased contact resistance and defects, which affects the integration density and performance of these devices.

Innovation Solution

The semiconductor device incorporates a seed layer with different grain sizes in its contact structures, where the lower region has a first grain size and the upper region is amorphous or has a smaller grain size, allowing for a contact plug with a second grain size that reduces resistance by increasing the mean free path, and an ion implantation process adjusts the grain size to optimize conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the critical dimension of contacts is decreased to increase integration density, then the integration density is improved, but the contact resistance increases and defects occur

Engineering Contradiction:

Improveintegration densityVSAvoidcontact resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by creating a seed layer with non-uniform grain size distribution - the lower region has a first grain size while the upper region has a second grain size that is amorphous or has a different grain size. This local variation in microstructure optimizes electrical conductivity at the contact interface while maintaining structural integrity, thereby reducing contact resistance despite smaller contact dimensions.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of grain size within the seed layer to optimize contact properties. By controlling the grain size to be amorphous or different in the upper region compared to the lower region, the material's electrical conductivity is enhanced, which reduces contact resistance and allows for smaller contact critical dimensions while maintaining reliability.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the grain size of the seed layer is increased to reduce contact resistance, then the contact resistance is improved, but the contact structure complexity increases

Engineering Contradiction:

Improvecontact resistanceVSAvoidcontact structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the seed layer into distinct regions with different grain sizes - a lower region with a first grain size and an upper region with a second grain size that is amorphous or has a different grain size. This segmentation allows each region to fulfill specific functions: the lower region provides structural support while the upper region optimizes electrical conductivity, achieving low contact resistance without requiring complex overall contact structures.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in low-resistance contact structures and interconnection lines, enhancing the performance and reliability of semiconductor devices by reducing contact resistance and defects associated with smaller critical dimensions.

Implementation Method 1

an ion implantation process adjusts the grain size to optimize conductivity

Methodology Applied

Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

a contact plug on an upper region of the seed layer and having a second grain size, and having a mean free path that is increased

Methodology Applied

Scientific EffectGrain size control:

Data Source

PatentUS11837645B2Method of manufacturing a semiconductor device

Publication Date: 2023.12.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.