Semiconductor Contact Structure With Height Offset for Isolation
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Solution Overview
Problem
The existing semiconductor structures formed by self-aligned contact processes face performance limitations due to short-circuit issues and increased parasitic capacitance, which affect the electrical performance and efficiency of semiconductor devices as they are developed towards higher integration and smaller sizes.
Innovation Solution
A semiconductor structure and fabrication method that include a substrate with multiple gate structures and source-drain doped layers, a conductive structure with a specific height configuration, and an isolation layer to reduce short-circuits and parasitic capacitance, improving electrical performance and production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned contact process is used to form conductive structure, then manufacturing precision is improved, but parasitic capacitance increases
Solution Approach 1:
The patent introduces a height dimension differentiation between conductive structures in different regions. The first conductive structure (gate contact) is formed at a first height, while the second conductive structure (source-drain contact) is formed at a second height lower than the first height. This vertical separation in the height dimension reduces parasitic capacitance between adjacent conductive structures while maintaining the self-aligned manufacturing process.
2Productivity
If device size is reduced for higher integration, then productivity is improved, but short-circuit issues increase
Solution Approach 1:
By utilizing the vertical height dimension to differentiate between gate contact and source-drain contact structures, the patent achieves electrical isolation between these conductive elements. The height difference creates physical separation that prevents short-circuits even when planar dimensions are reduced for higher integration density.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary material between the first and second conductive structures. This dielectric layer fills the trench formed between the conductive structures and provides electrical isolation, preventing short-circuits while allowing close proximity for high integration.
3Device complexity
If conductive structures are formed at same height, then device complexity is reduced, but electrical performance deteriorates
Solution Approach 1:
The patent resolves the electrical performance issue by introducing height differentiation. The first conductive structure extends to a first height and the second conductive structure extends to a second height lower than the first height. This vertical separation reduces parasitic capacitance and improves electrical performance without significantly increasing fabrication complexity, as the height control can be achieved through selective etching and filling processes.
Data Source
AI summary
A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.