Semiconductor Contact Etching for Cell-Core Height Matching
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Solution Overview
Problem
The miniaturization of semiconductor circuit patterns leads to challenges in the manufacturing process, particularly due to step differences between bit line and core areas, which complicates the etching process and affects process margins and subsequent wiring processes.
Innovation Solution
A method of fabricating a semiconductor device that involves defining cell and core areas, forming bit line and gate structures, and using a core capping film with a greater height than the bit line structure, followed by etching processes to ensure the bit line and core capping films have the same height, thereby eliminating step differences and facilitating subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If circuit patterns are miniaturized to accommodate more semiconductor elements, then integration density is improved, but step differences between cell area and core area increase causing process margin loss
Solution Approach 1:
The core capping film is formed with a greater height than the bit line structure in advance, before the etching process. This preliminary height difference is intentionally created to compensate for the step difference that will occur during subsequent etching, ensuring that the final heights match and process margins are maintained throughout the manufacturing process.
2Quantity of substance
If bit lines are formed in cell area with higher integration, then quantity of elements is improved, but etching process complexity increases due to step differences
Solution Approach 1:
The height parameter of the core capping film is specifically changed to be greater than the bit line structure height. This parameter adjustment creates a controlled step difference that compensates for etching variations, simplifying the etching process by providing a built-in reference level and reducing the need for complex process control measures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures a process margin for both cell and core areas, enhances reliability by preventing pattern defects, and simplifies subsequent processes like wiring, while maintaining the integrity of bit line structures.
Implementation Method 1
etching the first contact film until a height of the first contact film is less than that of the bit line structure using an etching process. The etching rate for the first contact film is greater than the etching rates for the bit line structure and the core capping film.
Data Source
AI summary
A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.