Semiconductor Device Metallization Contact Hole Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device manufacturing is forming contact holes of differing depths simultaneously, which often results in etching damage to the thin layers at the bottom of shallower contact holes, reducing device reliability and increasing production complexity and costs.
Innovation Solution
The solution involves using two protective layers of different thicknesses, one thicker and one thinner, to prevent over-etching and damage during the etching process, allowing for the simultaneous formation of contact holes of varying depths by employing an etch stop layer configuration that maintains etch selectivity with respect to the insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact holes of differing depths are simultaneously formed through one etching process, then productivity is improved, but etching damage occurs in thin layers at the bottom of shallower contact holes
Solution Approach 1:
The patent applies local quality by providing different thicknesses of protective layers (first protective layer and second protective layer) at different locations corresponding to shallower and deeper contact holes. The thinner protective layer is provided for shallower contact holes while a thicker protective layer is provided for deeper contact holes, allowing each region to have the appropriate protection level needed for its specific etching depth requirements.
Solution Approach 2:
The patent implements beforehand cushioning by providing protective layers prior to the etching process. These protective layers act as a buffer that prevents etching damage to the thin layers at the bottom of contact holes during the simultaneous etching process, cushioning against the harmful effects of over-etching before they can occur.
2Reliability
If contact holes of differing depths are formed separately, then etching damage is reduced, but the number of processes increases
Solution Approach 1:
The patent merges multiple separate etching processes into a single simultaneous etching process by providing differentiated protective layers beforehand. This allows shallower and deeper contact holes to be formed in one process step rather than requiring separate processes, thereby improving productivity while maintaining reliability through the protective layer configuration.
Solution Approach 2:
The patent applies parameter changes by varying the thickness of protective layers (differentiating between first and second protective layers) to enable a single etching process to accommodate contact holes of differing depths. This parameter variation allows the etching process to reach different depths without causing damage to shallower regions, combining the benefits of separate processing with the efficiency of simultaneous processing.
3Device complexity
If a single protective layer is used for all contact holes, then the process is simplified, but over-etching damage occurs in shallower contact holes
Solution Approach 1:
The patent resolves this contradiction by applying local quality - instead of a uniform protective layer, it provides differentiated protective layers (first protective layer for shallower contact holes, second protective layer for deeper contact holes) with different thicknesses tailored to the specific requirements of each contact hole depth, preventing over-etching damage while maintaining reasonable process complexity.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.