Semiconductor Contact Hole Formation via Segmented Etching

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Solution Overview

Problem

The challenge lies in forming highly integrated semiconductor devices without requiring high-cost equipment, as current methods for forming fine patterns are limited and costly.

Innovation Solution

A method involving the formation of preliminary holes, dielectric patterns, barrier layers, sacrificial layers, and etch control patterns to create contact holes, where the arrangement and etch selectivity of these layers allow for the precise formation of second preliminary holes and subsequent contact holes, improving integration density without the need for expensive equipment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to form fine patterns, then manufacturing process simplicity is maintained, but integration density and contact hole precision deteriorate

Engineering Contradiction:
Improvecontact hole precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The contact hole formation process is divided into multiple stages: first preliminary holes are formed, then second preliminary holes are formed between dielectric patterns, and finally contact holes are etched. This segmentation allows each stage to be optimized independently, achieving high precision without requiring single-step complex equipment

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dielectric patterns are formed in advance to serve as masks and structural guides for subsequent etching steps. The preliminary holes are also formed before final contact hole creation, allowing precise positioning and control of the final contact hole geometry without requiring expensive real-time control equipment

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If high-cost equipment is used, then fine pattern formation capability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvefine pattern formation capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Dielectric patterns serve as intermediary structures that enable precise pattern formation through standard etching equipment. These patterns act as self-aligned masks and structural guides, allowing fine contact hole formation without requiring specialized high-cost equipment

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Sacrificial layers and temporary dielectric patterns are used that can be formed with standard equipment and then removed after serving their positioning function. This approach replaces the need for expensive persistent specialized equipment with inexpensive consumable structural elements

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Productivity

If contact holes are formed closer together, then integration density is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidcontact hole spacing control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The method uses asymmetric arrangement of dielectric patterns and etch control patterns to define contact hole positions. The patterns are strategically placed to provide self-alignment and spacing control, enabling narrow pitch contact holes through geometric constraints rather than requiring ultra-precise positioning equipment

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the integration density of semiconductor devices by forming contact holes with a narrower distance between them, thereby improving the device's reliability and reducing manufacturing costs.

Implementation Method 1

at least one of the sacrificial layer and the etch control patterns having an etch selectivity with respect to the barrier layer

Methodology Applied
Scientific EffectEtch selectivity:

Data Source

PatentUS9034765B2Methods of forming a semiconductor device
Publication Date: 2015.05.19 SAMSUNG ELECTRONICS CO LTD
  • US9034765B2 patent drawing
  • US9034765B2 patent drawing
  • US9034765B2 patent drawing

AI summary

A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.