Semiconductor Contact Holes Between Sidewall Spacers
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Solution Overview
Problem
As semiconductor devices shrink, traditional planar transistors face challenges such as the short channel effect and unreliable fabrication processes, while fin-FETs offer advantages like lower ion concentration fluctuations and higher carrier mobility, but existing self-alignment methods for forming contact holes in semiconductor structures often result in size deviations, affecting connection performance.
Innovation Solution
A method involving the formation of discrete gate structures, sidewall spacers, and protective layers on a semiconductor substrate, where contact holes are formed between neighboring sidewall spacers with a first protective layer covering the dielectric layer between gate structures, and metal plugs are inserted in these holes to improve alignment and reduce metal contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing self-alignment methods are used to form contact holes, then the fabrication process is simplified, but the contact hole size deviates from the designed value
Solution Approach 1:
The method performs preliminary actions by forming protective layers on the gate structures and dielectric layer before forming the contact holes. The protective layers are formed in advance to prevent damage and contamination during subsequent etching and metal plug formation processes, ensuring that the contact hole dimensions remain accurate while maintaining process simplicity
Solution Approach 2:
The protective layers serve as intermediary elements between the gate structures/dielectric layer and the contact holes. These intermediary protective layers prevent direct contact between potentially contaminating materials and the underlying structures, thereby maintaining contact hole size accuracy without complicating the overall fabrication process
2Ease of manufacture
If contact holes are formed using conventional methods, then the process is straightforward, but metal contamination occurs and connection performance is affected
Solution Approach 1:
The method applies preliminary anti-action by forming protective layers before the contact hole formation process. These protective layers preemptively prevent metal contamination from occurring during the etching and metal plug formation steps, thereby eliminating the harmful effect without adding significant process complexity
Solution Approach 2:
The protective layers act as intermediary barriers that prevent direct interaction between metal materials and the underlying dielectric or gate structures. This intermediary protection eliminates metal contamination while keeping the fabrication process straightforward
Data Source
AI summary
The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.