Semiconductor Contact Structures via Insulating Line Height
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Solution Overview
Problem
The challenge in semiconductor devices is to reduce contact resistance when connecting a contact plug with a small cross-sectional area to a lower capacitor electrode, as the limited contact area restricts the ability to lower contact resistance effectively.
Innovation Solution
The semiconductor device design includes a substrate with active regions, bit lines, insulating lines, and contact structures, where the insulating lines are formed to have higher upper surfaces than the bit lines, allowing for the formation of larger cross-sectional area contact structures that improve contact alignment and reduce misalignment, thereby enhancing contact between the contact structures and the capacitor electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cross-sectional area of the contact plug is reduced to accommodate high integration, then the device density increases, but the contact area with the lower capacitor electrode is limited and contact resistance cannot be lowered effectively
Solution Approach 1:
The contact structure is extended vertically to form multiple levels (first contact structures at lower level, second contact structures at higher level). This multi-level vertical arrangement increases the effective contact area with the lower capacitor electrode without increasing the horizontal footprint, thus maintaining high device density while improving contact resistance
Solution Approach 2:
The first and second contact structures are nested vertically, with the first contact structures positioned at a lower level and the second contact structures at a higher level. This nested configuration allows both contact structures to connect to the same lower capacitor electrode, effectively increasing the total contact area while maintaining a compact vertical space
Data Source
AI summary
A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.