Semiconductor Contact Layer Structure for Low-Resistance Interfaces

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving optimal optical-electrical characteristics and process stability, particularly in the design of light-emitting diodes, where contact resistance and interfacial compound formation affect efficiency and longevity.

Innovation Solution

The semiconductor device incorporates a specific structure with a first p-type or n-type layer containing oxygen and a second metal element, a first semiconductor layer, and a metal element-containing structure, optimized with a thickness of the p-type or n-type layer less than or equal to 20 nm, and an insulating layer, which improves contact resistivity and prevents interfacial compound formation, enhancing the device's optical-electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional semiconductor device structure is used, then the device can be manufactured with standard processes, but the contact resistance is high and optical-electrical characteristics are suboptimal

Engineering Contradiction:
Improveoptical-electrical characteristicsVSAvoidlayer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is divided into multiple functional layers including a first semiconductor layer, a second semiconductor layer, a p-type or n-type layer, and an insulating layer. This segmentation allows each layer to be optimized for specific functions, improving overall optical-electrical characteristics while managing complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A p-type or n-type layer containing oxygen and a second metal element is introduced as an intermediary layer between the first semiconductor layer and the metal element-containing structure. This intermediate layer reduces contact resistance and prevents interfacial compound formation, resolving the contradiction between reliability and manufacturing complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the p-type or n-type layer thickness is increased, then contact resistance may be reduced, but interfacial compound formation increases and process stability decreases

Engineering Contradiction:
Improvecontact resistanceVSAvoidprocess stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The thickness of the p-type or n-type layer is precisely controlled to be less than or equal to 20 nm. This parameter optimization achieves low contact resistance while preventing excessive interfacial compound formation and maintaining process stability. The oxygen content and metal element composition are also optimized to balance these competing requirements

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If standard metal element-containing structures are used, then manufacturing is simpler, but interfacial compound formation occurs and device longevity is reduced

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoiddevice longevity
Core Design Contradiction:
Ease of manufactureVSDuration of action of stationary object

Solution Approach 1:

The p-type or n-type layer containing oxygen and a second metal element serves as a protective intermediary between the semiconductor layer and the metal electrode. This intermediate layer prevents direct contact between reactive metals and semiconductor materials, avoiding harmful interfacial compound formation and extending device lifespan while remaining compatible with standard manufacturing processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250015246A1Semiconductor device and semiconductor component including the same
Publication Date: 2025.01.09 ENNOSTAR CORP
  • US20250015246A1 patent drawing
  • US20250015246A1 patent drawing
  • US20250015246A1 patent drawing

AI summary

A semiconductor device is provided, which includes an active region, a first semiconductor layer, a first metal element-containing structure, a first p-type or n-type layer, a second semiconductor layer and an insulating layer. The active region has a first surface and a second surface. The first semiconductor layer is at the first surface. The first metal element-containing structure covers the first semiconductor layer and comprising a first metal element. The first p-type or n-type layer is between the first semiconductor layer and the first metal element-containing structure. The second semiconductor layer is between the first semiconductor layer and the first p-type or n-type layer. The insulating layer covers a portion of the first semiconductor layer and a portion of the second semiconductor. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm.