Semiconductor Contact Layer for Low Resistance
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Solution Overview
Problem
Conventional semiconductor manufacturing methods fail to reduce contact resistance effectively between the source/drain extension region and the metal silicide layer, leading to performance degradation due to high temperature annealing processes that alter the metal silicide's structure and increase resistivity.
Innovation Solution
A method involving the formation of a thin contact layer made of CoSi2, NiSi, or Ni(Pt)Si2-y on both the source/drain region and source/drain extension region, with a thickness less than 10 nm, which maintains thermal stability during high temperature processing and reduces contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal silicide layer is formed on the source/drain region to reduce contact resistance, then contact resistance is reduced, but the metal silicide layer cannot withstand high temperature annealing (600°C-800°C) required for high K gate dielectric layer, causing structure change and resistivity increase
Solution Approach 1:
A thin contact layer (5-10 nm) of CoSi2, NiSi, or Ni(Pt)Si2-y is formed on the source/drain extension region before the high temperature annealing process. This preliminary formation of a thermally stable contact layer ensures that when subsequent high temperature annealing (600°C-800°C) is performed for high K gate dielectric layer repair, the contact layer maintains its low resistivity and structural integrity, unlike conventional metal silicide layers that would degrade at these temperatures.
Solution Approach 2:
The invention changes the material parameters by selecting specific materials (CoSi2, NiSi, Ni(Pt)Si2-y) with higher thermal stability than conventional metal silicides. Additionally, the thickness parameter is controlled to be very thin (5-10 nm), which contributes to the overall thermal stability and performance of the contact structure during high temperature processing.
2Reliability
If the contact layer thickness is increased to reduce contact resistance, then contact resistance decreases, but short channel effects and leakage current increase
Solution Approach 1:
The invention optimizes the thickness parameter of the contact layer to a very thin range of 5-10 nm. This thin thickness is sufficient to provide low contact resistance while being thin enough to avoid significant short channel effects and leakage current. The specific material selection (CoSi2, NiSi, Ni(Pt)Si2-y) further enables this thin thickness to achieve the desired electrical performance without the harmful effects associated with thicker contact layers.
Data Source
AI summary
A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.