Semiconductor Contact Structure for Low-Capacitance Stable Contacts

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Solution Overview

Problem

As semiconductor devices scale down, there is a need to reduce capacitance and ensure electrical stability between contacts, which existing multi-gate transistors have not adequately addressed.

Innovation Solution

A semiconductor device design featuring a gate structure with a gate electrode and gate spacer spaced apart, a source/drain pattern, a contact barrier layer of titanium nitride, and a contact filling layer of tungsten, where the contact filling layer has distinct portions with varying widths and the contact barrier layer surrounds part of the filling layer, optimizing contact formation and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the pitch size of semiconductor device is decreased to increase density, then productivity is improved, but capacitance increases and electrical stability deteriorates

Engineering Contradiction:
Improvedevice densityVSAvoidelectrical stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact barrier layer is configured with different widths at different locations: a first width at the lower surface and a second width at the upper surface. This local variation in geometry allows optimization of electrical properties at different levels, reducing capacitance where critical while maintaining connectivity where needed, thus resolving the contradiction between high density and electrical stability

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240405090A1Semiconductor device
Publication Date: 2024.12.05 SAMSUNG ELECTRONICS CO LTD
  • US20240405090A1 patent drawing
  • US20240405090A1 patent drawing
  • US20240405090A1 patent drawing

AI summary

A semiconductor device is provided. The semiconductor device includes: a semiconductor device including: an active pattern extending in a first direction; a gate structure including a gate electrode extending in a second direction and a gate spacer on the active pattern, wherein the gate electrode and the gate spacer are spaced apart from each other in the first direction; a source/drain pattern on the active pattern; a contact barrier layer on the source/drain pattern; and a contact filling layer on the contact barrier layer. An uppermost point of the contact barrier layer is between an upper surface of the contact filling layer and a lower surface of the contact filling layer, and outer walls of the contact barrier layer and outer walls of the contact filling layer extend along a common plane.