Semiconductor Interconnection Contact Metallization Stress Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Precision analog integrated circuits are sensitive to mechanical stresses during fabrication and assembly, particularly due to metallization-induced stress near p-n junctions, which can cause instability and degrade electrical performance by altering transistor characteristics.
Innovation Solution
The method involves depositing a diffusion barrier layer, such as TiW, and an Al-based metallization layer on semiconductor devices, then removing the metallization from critical areas near p-n junctions to reduce mechanical stress, with the diffusion barrier layer providing conductive paths to maintain device stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Al-based metallization is deposited over the entire interconnection area including near p-n junctions, then electrical conductivity and interconnection functionality are improved, but mechanical stress increases causing device instability and transistor mismatch
Solution Approach 1:
The patent removes the Al-based metallization layer from critical areas near p-n junctions while maintaining it in non-critical interconnection regions. This selective extraction eliminates the source of mechanical stress near sensitive junctions while preserving the electrical conductivity functions in areas where metal is needed.
Solution Approach 2:
The patent applies different metallization configurations to different regions: Al-based metallization is present in non-critical areas for conductivity, but absent in critical areas near p-n junctions to reduce stress. This local differentiation allows simultaneous optimization of electrical performance and device stability.
2Manufacturing precision
If Al-based metallization is used for interconnections, then electrical conductivity is improved, but device matching precision deteriorates due to stress-induced transistor characteristic changes
Solution Approach 1:
The harmful Al-based metallization is extracted from critical regions near p-n junctions where it generates stress that degrades transistor matching. The diffusion barrier layer remains to provide necessary electrical connection without introducing the harmful stress effects.
Solution Approach 2:
The patent converts the potentially harmful presence of metallization near junctions into a beneficial configuration by selectively removing it from stress-sensitive areas while maintaining it in areas where its conductive benefit is needed, thus transforming a source of device degradation into a controlled design feature.
3Reliability
If complete metallization coverage is maintained for electrical connection, then electrical conductivity is improved, but device stability during temperature treatment deteriorates
Solution Approach 1:
The patent implements spatially varying metallization coverage: complete coverage in non-critical areas maintains electrical connectivity, while selective removal in critical areas near p-n junctions ensures temperature stability. The diffusion barrier layer provides the necessary local electrical connection where Al metal is absent.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces mechanical stress and maintains transistor matching accuracy, ensuring higher stability and precision in semiconductor devices by eliminating metallization-induced errors, particularly in temperature-treated circuits.
Implementation Method 1
A diffusion barrier layer, typically a homogeneous metal such as titanium-tungsten (TiW) is deposited over the devices
Implementation Method 2
The diffusion barrier and metallization layers are masked and etched to define interconnection traces. Then, mask and etch steps are performed so as to remove interconnection trace metallization that is in close proximity to at least one of the p-n junctions
Data Source
AI summary
A semiconductor device interconnection contact and fabrication method comprises fabricating one or more active devices on a semiconductor substrate. A diffusion barrier layer is deposited over the devices, followed by an Al-based metallization layer. The diffusion barrier and metallization layers are masked and etched to define interconnection traces. Mask and etch steps are then performed to remove interconnection trace metallization that is in close proximity to the active device regions, while leaving the traces' diffusion barrier layer intact to provide conductive paths to the devices, thereby reducing metallization-induced mechanical stress which might otherwise cause device instability.