Semiconductor Contact Structure for Mixed Channel-Length Transistors
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Solution Overview
Problem
In semiconductor manufacturing, the coexistence of long-channel and short-channel gate structures in a semiconductor structure leads to performance reduction due to increased channel leakage current and contact resistance issues.
Innovation Solution
A semiconductor structure is designed with a first region having long-channel gate structures and a second region with short-channel gate structures, where a first barrier layer with a lower etching rate than the dielectric layer is used to form openings that expose source-drain doped layers, thereby reducing etching time and preventing layer penetration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long-channel gate structure is introduced to reduce the short-channel effect, then channel leakage current is suppressed, but device area increases and manufacturing complexity increases
Solution Approach 1:
The semiconductor device is divided into a first region with long-channel gate structures and a second region with short-channel gate structures. This segmentation allows different channel length strategies to be applied in different areas, suppressing channel leakage in the first region while maintaining high integration in the second region, thereby resolving the contradiction between reliability and device complexity.
Solution Approach 2:
Different gate structures are applied locally to different regions: long-channel gates in the first region for leakage suppression, and short-channel gates in the second region for high density. This local differentiation enables each region to optimize its performance characteristics without compromising the other, balancing reliability and manufacturing complexity.
2Manufacturing precision
If etching is performed to form openings in the dielectric layer, then source-drain doped layers are exposed, but etching time increases and layer penetration risk increases
Solution Approach 1:
A barrier layer is introduced as an intermediary between the dielectric layer and the source-drain doped layer. This barrier layer has different etching characteristics than the dielectric layer, allowing the etching process to be better controlled. The barrier layer acts as a mediator that protects against over-etching and penetration while enabling precise opening formation, thus improving manufacturing precision without excessive time loss.
3Productivity
If transistor critical size is shrunk to increase integration degree, then device area decreases, but channel leakage current increases due to short-channel effect
Solution Approach 1:
The device is segmented into regions with different gate structures. The first region uses long-channel gates to suppress leakage, while the second region uses short-channel gates for high integration. This segmentation resolves the contradiction by allowing both high integration and leakage suppression to coexist in different areas of the same device.
Solution Approach 2:
The channel length parameter is changed differently in different regions: longer channel length in the first region to suppress leakage, and shorter channel length in the second region to maintain high integration. This parameter differentiation allows the device to achieve both high productivity and reliability simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution improves the performance of the semiconductor structure by reducing channel leakage current and contact resistance, enhancing the overall performance of the semiconductor device.
Implementation Method 1
a first barrier layer with a lower etching rate than the dielectric layer is used to form openings that expose source-drain doped layers
Data Source
AI summary
A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, first gate structures, second gate structures, first source-drain doped layers, second source-drain doped layers, and a first dielectric layer. A top surface of the first dielectric layer disposed over the first region is lower than a top surface of the first dielectric layer disposed over the second region. The semiconductor structure also includes a first barrier layer disposed over the first dielectric layer disposed over the first region. The first barrier layer and the first dielectric layer disposed over the first region include a first opening exposing the first source-drain doped layer, and the first dielectric layer disposed over the second region includes a second opening exposing the second source-drain doped layer.