Semiconductor Contact Structure With Sidewall Pad Pattern

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Solution Overview

Problem

The challenge in semiconductor device fabrication is to achieve denser integration while maintaining improved electrical characteristics, as the reduction in size and increased integration density pose limitations on pattern definition and component spacing.

Innovation Solution

The semiconductor device design includes a gate structure with dopant regions, conductive lines, and contact structures featuring a pad pattern with sidewall portions and a spacer structure with an air gap, which enhances electrical connectivity and minimizes parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the spacing between constituent parts is reduced to achieve denser integration, then integration density increases, but manufacturing precision and pattern definition become more difficult

Engineering Contradiction:
Improveintegration densityVSAvoidpattern definition
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The contact structure is segmented into multiple components: a contact hole portion, a pad pattern with bottom portion and sidewall portions, and a conductive fill. This segmentation allows each component to be optimized independently - the pad pattern's extended sidewall portions increase contact area without requiring smaller spacing between devices, thus maintaining manufacturing precision while achieving denser integration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pad pattern extends in the vertical dimension with sidewall portions that protrude laterally from the contact hole. This dimensional extension increases the contact area between the contact structure and the doped region without reducing the horizontal spacing between adjacent devices, thereby achieving higher integration density while maintaining manufacturability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the contact area is increased to improve electrical characteristics, then electrical conductivity improves, but device area increases reducing integration density

Engineering Contradiction:
Improveelectrical characteristicsVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The pad pattern utilizes the vertical and lateral dimensions by extending sidewall portions upward and outward from the contact hole base. This three-dimensional configuration increases the effective contact area with the doped region, improving electrical characteristics, while the contact structure occupies minimal horizontal footprint, preserving integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The pad pattern is nested within the contact hole structure, with the bottom portion filling the contact hole and sidewall portions extending laterally. This nested configuration maximizes contact area within a compact footprint, improving electrical connectivity without proportionally increasing the device area.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If parasitic capacitance is reduced to improve electrical characteristics, then signal integrity improves, but contact area may be reduced

Engineering Contradiction:
Improvesignal integrityVSAvoidcontact area
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

Air gaps are introduced by removing dielectric material between adjacent contact structures. This extraction of material creates low-capacitance regions that reduce parasitic coupling between neighboring contacts, improving signal integrity. The air gaps are strategically placed in regions where material removal does not compromise the contact area between the pad pattern and the doped region.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The contact structure exhibits local quality variations: the pad pattern has large contact area with the doped region for low contact resistance, while air gaps are introduced in inter-contact regions for low parasitic capacitance. This spatial differentiation of properties allows simultaneous optimization of both contact area and parasitic capacitance reduction.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9178026B2Semiconductor devices and methods fabricating same
Publication Date: 2015.11.03 SAMSUNG ELECTRONICS CO LTD
  • US9178026B2 patent drawing
  • US9178026B2 patent drawing
  • US9178026B2 patent drawing

AI summary

Disclosed are semiconductor devices and methods of forming the same. According to the semiconductor device, gate structures are provided to be buried in a substrate and first dopant regions and second dopant regions are provided at both ends of the gate structures. Conductive lines cross the gate structures and are connected to the first dopant regions. Contact structures are respectively provided in contact holes which are provided between the conductive lines and expose the second dopant regions. The contact structures are in contact with the second dopant regions, respectively. Each of the contact structures includes a pad pattern extending along a sidewall of the contact hole.