Semiconductor Contact Plug Alignment and Bit Line Capacitance Reduction
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Solution Overview
Problem
The increasing integration of memory devices leads to reduced overlay margins between contact plugs and bit lines, causing misalignment and leakage current, as well as increased capacitance due to residual etch stop layers between bit lines.
Innovation Solution
A semiconductor device manufacturing method involving an interlayer insulating layer with openings, where contact plugs are formed using a first conductive layer in lower portions and bit lines using a second conductive layer in upper portions, coupled within the interlayer insulating layer, preventing misalignment and reducing capacitance by eliminating the etch stop layer between bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If overlay margin between contact plugs and bit lines is reduced due to limited cell area, then integration density is improved, but misalignment between contact plugs and bit lines occurs causing leakage current
Solution Approach 1:
The patent applies preliminary action by forming a mandrel pattern before contact hole etching that defines both the contact plug position and the bit line position. This pre-established reference structure ensures accurate alignment between contact plugs and bit lines even when overlay margin is reduced, preventing misalignment and leakage current while maintaining high integration density
2Ease of manufacture
If etch stop layer is used during manufacturing, then etching process control is improved, but capacitance between bit lines increases due to residual etch stop layer
Solution Approach 1:
The patent extracts and removes the etch stop layer completely after it has served its purpose as an etching reference during contact hole formation. By removing the etch stop layer before bit line formation, the harmful capacitance effect is eliminated while the beneficial etching control is preserved during the critical contact hole etching process
Data Source
AI summary
A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer.