Semiconductor Contact Plug Metal Barrier Layer
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Solution Overview
Problem
Conventional DRAMs face challenges in ensuring sufficient capacitor capacity and reducing contact resistance due to limited plan-area for capacitors, misalignment of capacitor holes, and abnormal silicidation reactions, which hinder high-performance memory operation and increase manufacturing complexity.
Innovation Solution
The semiconductor device incorporates a metal barrier layer with a multi-layered structure, such as tungsten nitride and tungsten silicide, to prevent abnormal silicidation reactions and ensure a large contact area between the capacitor contact plug and bottom electrode, while maintaining a high yield in manufacturing. This is achieved by forming a metal-polysilicon interface with a larger area than the metal-metal interface, allowing for effective contact even with misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the plan-area for the capacitor is limited to shrink memory cells, then the degree of integration is improved, but the capacitor capacity is reduced
Solution Approach 1:
The capacitor structure transitions from a planar configuration to a three-dimensional configuration by forming the bottom electrode on the side wall of the capacitor hole. This vertical extension into the third dimension allows the capacitor to achieve sufficient capacity within the limited planar area, resolving the contradiction between integration density and capacitor capacity.
2Quantity of substance
If the capacitor hole depth is increased to ensure necessary capacitor capacity, then the capacitor capacity is improved, but the contact area between bottom electrode and capacitor contact plug is reduced
Solution Approach 1:
Instead of increasing hole depth which reduces contact area, the bottom electrode is formed on the side wall of the capacitor hole, extending the electrode area into the vertical dimension. This provides sufficient contact area with the capacitor contact plug while maintaining the required capacitor capacity through the side wall electrode configuration.
3Reliability
If a metal barrier layer is added to prevent abnormal silicidation, then the reliability is improved, but the device complexity is increased
Solution Approach 1:
A metal barrier layer is introduced as an intermediary between the capacitor contact plug and the bottom electrode. This barrier layer prevents direct contact between reactive materials, thereby preventing abnormal silicidation reactions. Although it adds a layer, it simplifies the overall process by preventing defects that would require additional corrective steps.
Data Source
AI summary
A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.