Semiconductor Contact Plug Bridge Prevention
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Solution Overview
Problem
The challenge in manufacturing 3-dimensional nonvolatile memory devices is the difficulty in forming contact plugs with varying depths, which can lead to process complexity and the risk of bridge formation due to the contact plug passing through word lines.
Innovation Solution
A semiconductor device with alternately stacked conductive and insulating layers, where each conductive layer has distinct thickness regions, and a method involving sacrificial layers and slit formations to create openings for conductive layer formation, preventing bridge formation by selectively increasing the thickness of pad regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to pass through word lines to connect to stacked memory cells, then electrical connection to memory cells is achieved, but bridge formation may occur and process difficulty increases
Solution Approach 1:
The contact plug formation process is segmented into multiple stages: first forming contact plugs for upper memory cells, then selectively removing sacrificial layers, and finally forming contact plugs for lower memory cells. This segmentation prevents bridge formation by ensuring that contact plugs are formed in discrete steps rather than attempting to pass through all word lines simultaneously.
Solution Approach 2:
Sacrificial layers are formed in advance between the conductive layers before the contact plug formation process. These sacrificial layers serve as placeholders that guide the subsequent etching and contact plug formation, ensuring that contact plugs are formed at the correct positions without bridging adjacent conductive layers.
2Adaptability or versatility
If contact plugs of various depths are formed to reach different memory cell levels, then connection to multiple stacked memory cells is achieved, but manufacturing process difficulty increases
Solution Approach 1:
The conductive layers are designed with varying local thicknesses to create pad regions with different heights. Contact plugs are formed to connect to these locally varied pad regions, allowing connection to multiple memory cell levels. This local quality variation simplifies the manufacturing process compared to forming contact plugs of precisely controlled various depths, as the thickness variation is achieved through the layer deposition process itself rather than complex etching control.
Solution Approach 2:
Sacrificial layers serve as intermediaries during the contact plug formation process. They are formed between the conductive layers, allowing contact plugs to be formed at different depths by selectively removing these sacrificial layers. This intermediary approach simplifies the overall process by providing a clear template for contact plug formation at multiple levels.
3Ease of manufacture
If conductive layers have uniform thickness, then manufacturing process is simplified, but ability to prevent bridge formation and create stable structure is reduced
Solution Approach 1:
Conductive layers are formed with different local thicknesses, creating pad regions that are thicker than the cell regions. This local quality variation provides structural stability by creating broader support areas (pad regions) that prevent bridge formation between adjacent contact plugs, while the thinner cell regions allow for precise memory cell formation. The thickness variation is integrated into the layer deposition process, maintaining manufacturing simplicity.
Data Source
AI summary
The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.