Semiconductor Contact Plug Capping Pattern Planarization

Solution Overview

Problem

The self-aligned contact (SAC) technique for semiconductor devices faces challenges in achieving satisfactory etch selectivity between interlayer insulation layers and capping patterns, leading to insufficient shoulder margins and increased leakage between gate electrodes and contact plugs, especially as design rules tighten with higher integration.

Innovation Solution

The method involves forming a capping pattern and interlayer insulation layer, followed by chemical mechanical polishing (CMP) to planarize the upper surface, using a slurry with controlled polishing speeds and selectivity to maintain a robust shoulder margin and prevent excessive etching, thereby ensuring reliable contact plug formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If over etching is performed to prevent Not Open (N/O) of the semiconductor substrate between the gates during the formation of the opening, then the opening can be fully formed, but the thickness of a shoulder portion between the top portion and sidewall of the capping pattern becomes weaker

Engineering Contradiction:

Improveopening formation completenessVSAvoidshoulder portion thickness

Core Design Contradiction:

Manufacturing precisionVSStrength

Solution Approach 1:

The method performs preliminary planarization of the capping pattern's upper surface using CMP before forming the opening. This preliminary action creates a flat top surface that allows subsequent etching to proceed uniformly, preventing the need for excessive etching that would compromise the shoulder portion thickness while still ensuring complete opening formation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention changes the physical state and surface parameters of the capping pattern by applying CMP processing. This transforms the upper surface from a non-planar state to a planar state, which fundamentally alters how the subsequent etching process interacts with the capping pattern, enabling precise control over etching depth and protecting the shoulder portion.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If the shoulder portion of the capping pattern is further etched during additional plug formation, then the additional plug can be formed, but the additional plug and the gate electrode become electrically connected, causing device failure

Engineering Contradiction:

Improveadditional plug formationVSAvoidelectrical isolation between gate electrode and additional plug

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The method performs preliminary planarization of the capping pattern's upper surface using CMP before forming the opening. This preliminary action creates a flat top surface that allows subsequent etching to proceed uniformly, preventing the need for excessive etching that would compromise the shoulder portion thickness while still ensuring complete opening formation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

By planarizing the upper surface beforehand, the invention creates a cushion or buffer that prevents over-etching from reaching the gate electrode. The planar surface ensures that etching stops at a predictable depth, maintaining the shoulder portion as a protective barrier that prevents electrical connection between the additional plug and gate electrode.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If design rule is reduced due to higher integration, then device integration increases, but the shoulder margin of the capping pattern decreases

Engineering Contradiction:

Improvedevice integration levelVSAvoidshoulder margin

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The invention changes the physical state and surface parameters of the capping pattern by applying CMP processing. This transforms the upper surface from a non-planar state to a planar state, which fundamentally alters how the subsequent etching process interacts with the capping pattern, enabling precise control over etching depth and protecting the shoulder portion.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the shoulder margin of the capping pattern, reduces leakage between gate electrodes and contact plugs, and maintains reliability even with further etching, improving the manufacturing process and device performance.

Implementation Method 1

Removing a portion of the capping pattern and the interlayer insulation layer may include polishing the capping pattern and the interlayer insulation layer using a chemical mechanical polishing (CMP) method

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS8084344B2Methods of fabricating a semiconductor device

Publication Date: 2011.12.27 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.