Semiconductor Contact Plug Formation via Etch Back
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Solution Overview
Problem
In semiconductor devices with vertical MOS transistors, the formation of contact plugs for embedded bit lines and word lines poses a risk of short-circuiting due to insufficient depth and margin between the contact plugs and the semiconductor substrate, particularly in the peripheral circuit region, where the relative positional relationship between the embedded bit lines and word lines complicates the etching process.
Innovation Solution
A method is developed to form a first conductive layer buried in cavities on the semiconductor substrate, with an etch back process creating conductive portions at the bottom corners and sides, and forming a wider and deeper insulating section to embed the word line contact plug, ensuring a sufficient margin between the contact plug and the substrate without additional photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to connect embedded bit lines and word lines in peripheral circuit region, then electrical connection is achieved, but short-circuiting risk increases due to insufficient depth and margin between contact plugs and semiconductor substrate
Solution Approach 1:
The patent divides the contact plug formation process into separate etching steps for bit line contact plugs and word line contact plugs. This segmentation allows each contact plug type to be formed with optimized etching parameters, ensuring sufficient depth and margin for short-circuit prevention while managing process complexity through systematic division of the fabrication sequence
Solution Approach 2:
The patent performs preliminary etching of bit line contact plugs before forming word line contact plugs. This preliminary action establishes a depth reference and ensures that the first contact plugs achieve adequate margin from the semiconductor substrate before subsequent word line contact plugs are formed, preemptively addressing short-circuit risks
2Reliability
If etching depth is increased to prevent short-circuiting, then reliability improves, but manufacturing precision requirements increase due to need for exact depth control
Solution Approach 1:
The patent employs excessive etching action by forming bit line contact plugs to extend beyond the embedded bit line depth, creating a deliberate over-etch that ensures sufficient margin from the semiconductor substrate. This partial excessive action provides a safety buffer that accommodates etching variability while maintaining reliable isolation
Solution Approach 2:
The patent introduces an intermediary insulating film layer between the bit line contact plugs and the semiconductor substrate. This intermediary layer acts as a buffer that reduces the sensitivity to etching depth variations, allowing contact plugs to be formed with adequate isolation even when etching depth control has some variability
3Reliability
If different etching depths are used for bit line and word line contact plugs, then short-circuit prevention is achieved, but device complexity increases due to multiple etching steps
Solution Approach 1:
The patent segments the contact plug formation into distinct sequential steps: first forming bit line contact plugs with one etching depth, then forming word line contact plugs with a different etching depth. This segmentation enables each contact plug type to have optimized depth characteristics for short-circuit prevention while maintaining clear process boundaries that facilitate manufacturing
Solution Approach 2:
The patent performs preliminary formation of bit line contact plugs with greater etching depth before forming word line contact plugs. This preliminary action with excessive etching depth for bit line contacts establishes a foundation that ensures adequate margin, allowing subsequent word line contact plugs to be formed with different depth characteristics without compromising overall reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable prevention of short-circuiting between the semiconductor substrate and contact plugs, enabling the formation of contact plugs of equal depth for both bit lines and word lines, thereby ensuring the integrity of the semiconductor device.
Implementation Method 1
subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity and a plurality of second conductive portions are formed at bottoms of the plurality of second cavities
Data Source
AI summary
Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.