Semiconductor Contact Plug Formation Using Germanium Epitaxial Layer
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming metal gates and contact plugs due to position shifts and penetration issues, affecting the electrical performance of devices as critical dimensions shrink.
Innovation Solution
A method involving the formation of a germanium layer on source/drain regions using selective epitaxial growth, which protects these regions during subsequent etching processes and ensures accurate plug formation without damaging the source/drain areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current photoresist and lithography techniques are used to form contact plugs and metal gates, then the manufacturing process can be maintained with existing equipment, but position shifts occur causing contact plugs to penetrate the metal gate and affecting electrical performance
Solution Approach 1:
The patent applies preliminary action by forming the contact plug structure before the metal gate structure in a reversed sequence. Specifically, the method forms a contact hole through the interlayer dielectric to expose the source/drain region, forms a contact plug, then forms the metal gate structure over the contact plug. This reversed sequence prevents position shift penetration issues because the contact plug is established first as a reference, and subsequent metal gate formation cannot penetrate through the already-formed contact plug structure.
2Length of moving object
If the critical dimension is continuously shrunk to achieve miniaturization, then the device size is reduced, but the position shift of contact plug increases and easily penetrates the metal gate
Solution Approach 1:
The patent applies inversion by completely reversing the conventional formation sequence of contact plugs and metal gates. Instead of forming contact plugs after metal gates, the method forms contact plugs first, then forms metal gates over them. This inverted sequence fundamentally changes the spatial and temporal relationship between the two structures, eliminating the penetration problem that occurs with continuous dimension shrinkage in conventional processes.
3Reliability
If a germanium layer is formed on source/drain regions using selective epitaxial growth, then the source/drain regions are protected during subsequent etching processes, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies the intermediary principle by introducing a germanium layer as a protective mediator between the source/drain region and the subsequent etching processes. The germanium layer is formed via selective epitaxial growth on the source/drain regions, creating a protective barrier that prevents damage during later manufacturing steps. This intermediary layer acts as a buffer that protects the underlying source/drain structures while being removable or integrable into the final device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The germanium layer effectively prevents exposure and damage to source/drain regions, enhancing the electrical performance of semiconductor devices by maintaining precise positioning and structure integrity.
Implementation Method 1
the present invention mainly performs a selective epitaxial growth process right after forming the opening of exposing the source/drain region, to form a germanium layer completely covering the top surfaces of the source/drain region
Data Source
AI summary
A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.


