Semiconductor Contact Plug Groove Formation
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the high precision required for lithography and patterning due to narrow array pitches of contact plugs, which can lead to short-circuiting and complexity in forming contact holes, especially in high-integration semiconductor devices like DRAMs.
Innovation Solution
The solution involves forming a groove in the second inter-layer insulation film that extends in the same direction as the gate electrodes, exposing the top surface of the first contact plugs, and creating second contact plugs within this groove, allowing for easier patterning and integration with wiring patterns, eliminating the need for forming minute contact holes and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional contact hole formation method is used, then contact plugs can be formed, but high precision lithography and patterning are required which increases manufacturing complexity and risk of short-circuiting
Solution Approach 1:
The groove is formed in advance in the second inter-layer insulation film to expose the top surface of the first contact plug. This preliminary action eliminates the need for subsequent high-precision contact hole formation, as the groove already provides the necessary access to the contact plug top surface, thereby reducing manufacturing complexity while maintaining precision
Solution Approach 2:
The formation process is segmented into distinct steps: first forming the groove in the insulation film, then separately forming the second contact plug within the groove, and finally forming wiring patterns. This segmentation allows each step to be optimized independently, reducing the overall manufacturing complexity compared to the conventional single-step contact hole formation
2Productivity
If array pitch of contact plugs is reduced for high integration, then device integration increases, but short-circuiting risk increases and requires very high precision patterning
Solution Approach 1:
The groove acts as an intermediary structure between the first contact plug and the second contact plug/wiring pattern. By introducing this intermediate feature, the design provides built-in isolation and spacing control that prevents short-circuiting even when the array pitch is reduced for higher integration, thereby maintaining reliability while increasing productivity
Solution Approach 2:
The solution moves from a two-dimensional planar contact hole approach to a three-dimensional structure with vertical grooves. This dimensional change allows for better spatial separation and control of contact plugs at reduced pitches, preventing short-circuits while maintaining high integration density
Data Source
AI summary
There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, and a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insulation film and connected to either the source region or the drain region; a second inter-layer insulation film covering the first contact plug; a groove extending in the second inter-layer insulation film in a same direction as an extending direction of the gate electrode and exposing a top surface of the first contact plug at a bottom thereof; a second contact plug connected to the first contact plug and formed in the groove; and a wiring pattern extending on the second inter-layer insulation film so as to traverse the groove and integrated with the second contact plug.