Semiconductor Contact Plug Formation via Multi-Orientation Insulating Patterns
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Solution Overview
Problem
In highly integrated semiconductor devices, forming precise metal contact plugs with low resistance and high reliability is challenging due to issues like increased contact resistance, voids in contact plugs, and copper migration, especially when using the dual damascene process for miniaturized features.
Innovation Solution
A semiconductor device and method involving a unique arrangement of insulating patterns to expose metal lines, with a first insulating pattern and a third insulating pattern formed perpendicular to each other, allowing for a wider trench to be etched using these patterns as masks, enabling reliable contact plug formation without voids and preventing copper migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the contact hole size is reduced to increase integration density, then the integration density is improved, but the contact resistance increases and voids form in the contact plug
Solution Approach 1:
The patent transitions from forming contact holes in a single plane to creating a three-dimensional contact structure with multiple insulating patterns arranged in different orientations (first, second, and third insulating patterns). This dimensional approach allows the contact plug to maintain low resistance while accommodating higher integration density by exposing the metal line from multiple directions.
Solution Approach 2:
The contact structure is divided into multiple segments: first insulating pattern, second insulating pattern, and third insulating pattern, each serving specific functions. This segmentation allows precise control over the contact hole formation process, enabling the metal line to be exposed at multiple locations without compromising the overall contact resistance or creating voids.
2Speed
If the dual damascene process is used to form copper contact plugs, then the operating speed is improved, but voids form in the contact plug and copper migration occurs
Solution Approach 1:
The patent performs preliminary actions by forming multiple insulating patterns (first, second, and third) before the actual contact plug formation. These patterns are prepared in advance to create multiple exposure points for the metal line, ensuring that the subsequent copper filling process can proceed without voids or migration issues while maintaining high operating speed.
Solution Approach 2:
Different regions of the contact structure are given different properties through the use of multiple insulating patterns. The first insulating pattern, second insulating pattern, and third insulating pattern are strategically positioned to provide localized exposure of the metal line, allowing the copper contact plug to be formed with optimal quality in each region while maintaining overall reliability.
3Reliability
If the barrier metal layer is made thicker to prevent copper migration, then the copper migration prevention is improved, but the manufacturing precision is reduced due to miniaturization constraints
Solution Approach 1:
Instead of increasing the barrier metal layer thickness in a single dimension, the patent introduces a third dimension by forming multiple insulating patterns in different orientations. This approach provides additional spatial control over copper migration prevention without compromising the precision of contact hole formation, as the multiple patterns create multiple exposure points that distribute the stress and control the copper flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reliable formation of contact plugs with reduced resistance and prevents voids and copper migration, enabling high-speed, low-power semiconductor device operation and efficient application of the dual damascene process for smaller features.
Implementation Method 1
a copper (Cu) line is deposited by an electroplating process
Implementation Method 2
polished by a chemical mechanical polishing (CMP) process
Data Source
AI summary
The semiconductor device comprises a metal line configured to be buried in an interlayer insulation layer formed over a semiconductor substrate, a first insulating pattern configured to be formed over the interlayer insulating layer and the first metal line so that the first metal line is exposed, a second insulating pattern configured to be buried between the first insulating patterns so that the first metal line is exposed, and a third insulating pattern configured to be formed over the first insulating pattern and the second insulating pattern so that the first metal line is exposed, thereby reducing the resistance of a contact plug, such that it operates at high speed and requires low power consumption.