Semiconductor Contact Plug Structure for Reduced Resistance
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Solution Overview
Problem
Conventional semiconductor devices face issues with high resistance and electrical shorting due to the miniaturization of devices, leading to inferior performance and quality, particularly with poly-silicon gates and metal gate contact plugs.
Innovation Solution
A semiconductor structure is developed with a specific configuration including a substrate, transistors, inter-layer dielectric layers, and contact plugs, where the top surface of the first contact plug is higher than the gate, allowing for improved electrical connectivity and reduced shorting risks through precise formation of contact plugs and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional poly-silicon gate is used, then manufacturing process is simple, but device performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional poly-silicon to work function metals (such as tungsten, molybdenum, or their alloys). This material substitution eliminates boron penetration and depletion effects while maintaining gate control functionality, thereby improving device performance without significantly complicating the manufacturing process
Solution Approach 2:
The patent employs composite material structures in the gate region, including work function metal layers combined with high-k dielectric materials. This composite approach provides both the electrical performance benefits of work function metals and the enhanced gate control of high-k dielectrics, resolving the performance issues of conventional poly-silicon gates
2Reliability
If multiple contact plugs are used to connect source/drain, then electrical connectivity is improved, but resistance increases and electrical short risk increases
Solution Approach 1:
The patent introduces a vertical dimension to the contact plug structure by extending contact plugs through multiple inter-layer dielectric layers to different heights. The first contact plug extends to a first height, the second contact plug to a second height, and the third contact plug to a third height. This vertical differentiation allows optimized electrical pathways that reduce resistance and prevent electrical shorts between gate and source/drain
Solution Approach 2:
The patent applies different contact plug configurations at different locations: contact plugs connecting to source/drain regions have different structures than those connecting to the gate. This localized optimization ensures low resistance pathways for source/drain connections while maintaining proper isolation for gate connections, thereby reducing both resistance and electrical short risks
3Productivity
If device size is miniaturized, then device density increases, but electrical short between gate and contact plug becomes more frequent
Solution Approach 1:
The patent utilizes vertical dimensionality by forming contact plugs at different heights within the inter-layer dielectric structure. This vertical separation creates physical spacing that prevents electrical shorts between the gate and contact plugs even as horizontal device dimensions are miniaturized, thereby maintaining reliability while increasing device density
Solution Approach 2:
The patent segments the contact plug structure into multiple distinct elements (first, second, and third contact plugs) at different vertical levels. This segmentation allows independent optimization of each contact plug's position and connection, enabling miniaturization while maintaining proper electrical isolation and preventing shorts
Data Source
AI summary
The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.