Semiconductor Contact Plug Positioning via SADP Spacer Masks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming precise metal gate and contact plug structures due to position shifts and penetration issues, affecting the electrical performance of devices as critical dimensions shrink.
Innovation Solution
The use of a spacer self-aligned double patterning (SADP) process and a patterned mask layer to form fin-shaped structures and precise openings in dense and iso regions, enabling precise electrical connections between source/drain regions and metal gates without penetrating the gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current photoresist and lithography techniques are used to form metal gate and contact plug, then the manufacturing process is simple, but the position shift of contact plug occurs and it may penetrate the metal gate, affecting electrical performance
Solution Approach 1:
The patent divides the pattern formation process into multiple stages using spacer self-aligned double patterning (SADP). First, mandrels are formed and spacers are deposited to create intermediate patterns. Then, additional spacers are formed to achieve the final dense fin patterns. This segmentation allows precise control of contact plug positions without direct lithography patterning at the critical dimension.
Solution Approach 2:
The patent performs preliminary actions by forming spacers around mandrels before removing the mandrels. The spacers serve as pre-formed masks that define the precise locations of contact plugs and fins. This preliminary spacer formation establishes the critical dimensions and positions before the actual contact plug formation, preventing position shifts and penetration issues.
2Quantity of substance
If critical dimension is shrunk continuously for miniaturization, then the device integration density increases, but the position shift and penetration problems worsen
Solution Approach 1:
The patent employs self-aligned processes where spacers automatically form at precise locations relative to mandrels and existing structures. The spacer width is controlled by conformal deposition thickness, which provides inherent self-alignment and eliminates the need for separate alignment steps. This self-service mechanism ensures consistent contact plug placement accuracy even as critical dimensions shrink for higher integration density.
3Reliability
If conventional lithography is used for pattern transfer, then the process is straightforward, but the electrical performance of the device is affected due to position shifts
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate between the lithography pattern and the final contact plug positions. The spacers act as self-aligned masks that transfer the pattern with high precision, eliminating position shifts that would otherwise occur with direct lithography. This intermediary approach ensures reliable electrical performance while maintaining manufacturing feasibility through standardized spacer deposition processes.
Data Source
AI summary
A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.