Semiconductor Contact Plug Fabrication via Vertical Gate Nesting
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Solution Overview
Problem
As semiconductor devices scale down to the 10 nm node and beyond, the fabrication of contact plugs becomes increasingly challenging due to reduced contact areas and increased resistance, requiring more masks which can lead to operational degradation.
Innovation Solution
A method involving a substrate with a gate structure, forming a silicon layer, planarizing it, and using a replacement metal gate (RMG) process to transform the gate structure into a metal gate, while forming a contact plug on one side and a silicon layer on the other, to enhance contact area and reduce fabrication difficulties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact areas are reduced to scale down transistor size, then transistor density is improved, but resistance increases
Solution Approach 1:
The patent transitions from two-dimensional planar contact structures to three-dimensional vertical contact structures by forming contact plugs that extend through the gate structure to contact the source/drain regions. This vertical dimension compensates for the reduced planar contact area, maintaining adequate contact resistance while enabling smaller transistor footprints.
Solution Approach 2:
The contact plug is nested within the gate structure, with the gate material surrounding the contact plug. This nested configuration allows the contact to pass through the gate structure, effectively using the gate structure itself as part of the contact pathway and maximizing contact area in a compact volume.
2Area of stationary object
If more masks are used to fabricate contact plugs, then contact area can be maintained, but device complexity and operational reliability worsen
Solution Approach 1:
The gate structure serves multiple functions: it acts as the control electrode for the transistor and simultaneously serves as a structural framework that contains and guides the contact plug. This multi-functionality eliminates the need for separate contact definition masks, as the gate patterning process inherently defines the contact locations.
Solution Approach 2:
The patent merges the contact formation process with the gate formation process. By forming the contact plug within the gate structure during gate fabrication, the patent combines what would traditionally be separate fabrication steps into a unified process, reducing the total number of masks required.
3Reliability
If contact area is increased to reduce resistance, then resistance is improved, but device area and fabrication complexity worsen
Solution Approach 1:
The patent achieves increased contact area by extending the contact plug vertically through the gate structure rather than expanding it horizontally. This vertical extension provides additional contact area with minimal increase in device footprint, as the contact plug utilizes the height dimension already present in the gate structure.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.