Semiconductor Contact Structure With Selective PMOS Dopant Implantation
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Solution Overview
Problem
The increasing complexity of semiconductor manufacturing due to scaling down processes has led to challenges in improving processing and manufacturing of integrated circuits, particularly in reducing contact resistance and enhancing transistor performance in static random-access memory (SRAM) devices.
Innovation Solution
Implanting a higher concentration of p-type dopants, such as boron, into the source/drain regions of SRAM p-type metal-oxide semiconductor (PMOS) transistors to improve contact resistance and enhance pull-up transistor performance, using nanostructure channel FETs like gate all-around (GAA) FETs, and employing multi-patterning processes for precise feature formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation allows each step to be optimized independently, managing the complexity introduced by scaling while maintaining high functional density
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial mandrels and spacers that are later removed. These preliminary structures enable precise pattern formation and self-alignment in subsequent steps, reducing processing complexity despite scaling down dimensions
2Reliability
If higher concentration of p-type dopants is implanted into source/drain regions, then contact resistance is reduced and transistor performance is enhanced, but device complexity increases
Solution Approach 1:
The patent applies local quality by implanting dopants selectively in specific regions: higher concentration p-type dopants in source/drain regions of PMOS transistors, while maintaining different doping profiles in other areas. This localized doping approach reduces contact resistance where needed without unnecessarily complicating the entire device structure
Solution Approach 2:
The patent utilizes parameter changes by varying dopant concentration, type, and implantation energy across different regions and depths. Specifically, it implements higher concentration p-type dopant implantation in source/drain regions to reduce contact resistance, while adjusting other parameters in different areas to achieve optimal device performance without uniform complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower contact resistance, increased sigma (minimum variation for DC read/write failure), and improved SRAM read margin and Vmax, thereby enhancing device performance and reliability.
Implementation Method 1
an implantation process is performed to implant a dopant in the source/drain region
Data Source
AI summary
A method includes forming first and second semiconductor fins on a front side of a substrate, removing portions of the first and second semiconductor fins to expose first and second substrate portions, respectively, forming a first source/drain region over the first substrate portion, wherein the first source/drain region comprises an n-type epitaxial material, forming a second source/drain region over the second substrate portion, wherein the second source/drain region comprises a p-type epitaxial material, depositing a dielectric material over the first and second source/drain regions, forming an opening in the dielectric material to expose a portion of the first source/drain region and a portion of the second source/drain region, forming a mask on the exposed portion of the first source/drain region, performing an implantation process to implant a dopant in the second source/drain region, removing the mask, and depositing a conductive contact electrically connected to the first and second source/drain regions.