Semiconductor Contact Resistance Reduction via Pre-Annealing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become smaller, there is a need for an improved method to further lower contact resistance due to increased contact hole height and decreased open area, which existing methods have not effectively addressed.
Innovation Solution
A method involving pre-annealing and post-annealing processes to form metal silicide on doped regions, with pre-annealing performed before additional doping and post-annealing at a lower temperature after doping, to improve contact resistance without deteriorating N-type or P-type contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If contact hole dimensions are reduced to enable smaller semiconductor devices, then device scaling is achieved, but contact resistance increases
Solution Approach 1:
A pre-annealing process is performed before the additional doping step to repair damage caused by contact hole etching. This preliminary action restores the crystal structure and reduces defects in the doped region, creating a better foundation for subsequent doping and silicide formation, ultimately lowering contact resistance despite reduced contact hole dimensions
Solution Approach 2:
The patent employs a two-stage annealing approach with different temperature parameters: a pre-annealing process at a first temperature followed by a post-annealing process at a second temperature. This parameter variation optimizes both damage repair and dopant activation, enabling effective contact resistance reduction in scaled devices
2Reliability
If additional doping is performed to reduce contact resistance, then contact resistance improves, but dopant diffusion increases
Solution Approach 1:
The pre-annealing process is conducted before additional doping to repair etching damage and prepare the crystal structure. This preliminary preparation enables more efficient dopant incorporation with reduced diffusion during the subsequent doping step, as the repaired lattice provides better dopant sites
Solution Approach 2:
The patent implements a continuous process sequence where pre-annealing, additional doping, and post-annealing are performed in succession without interruption. This continuous action ensures that the dopant concentration is maintained and activated effectively while minimizing diffusion through optimized timing and temperature control throughout the process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the contact resistance of semiconductor devices, improving operation speed and reducing leakage by optimizing the doping and annealing processes, specifically by minimizing dopant diffusion and repairing damage from contact etching.
Implementation Method 1
performing a pre-annealing process before an additional doping process and performing a post-annealing process after the additional doping process
Data Source
AI summary
The present invention provides a method for fabricating a semiconductor device capable of improving the contact resistance. According to an embodiment of the present invention, the method for fabricating the semiconductor device comprises: forming a doped region by doping and activation annealing a first dopant on a substrate; forming an interlayer insulating layer on the substrate; forming a contact hole exposing the doped region by etching the interlayer insulating layer; exposing the doped region to a pre-annealing; forming an additional doped region by doping a second dopant on a pre-annealed doped region; exposing the additional doped region to a post-annealing; and forming metal silicide on the additional doped region.